Issued Patents All Time
Showing 51–75 of 552 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10916471 | Dual silicide liner flow for enabling low contact resistance | Praneet Adusumilli, Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2021-02-09 |
| 10916650 | Uniform bottom spacer for VFET devices | Steven R. Bentley, Cheng Chi, Chanro Park, Ruilong Xie | 2021-02-09 |
| 10916468 | Semiconductor device with buried local interconnects | Effendi Leobandung | 2021-02-09 |
| 10916640 | Approach to high-k dielectric feature uniformity | Chun Wing Yeung, Chen Zhang | 2021-02-09 |
| 10903365 | Transistors with uniform source/drain epitaxy | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2021-01-26 |
| 10892331 | Channel orientation of CMOS gate-all-around field-effect transistor devices for enhanced carrier mobility | Myung-Hee Na | 2021-01-12 |
| 10872954 | Sidewall image transfer nanosheet | Effendi Leobandung | 2020-12-22 |
| 10854733 | Composite spacer enabling uniform doping in recessed fin devices | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2020-12-01 |
| 10840345 | Source and drain contact cut last process to enable wrap-around-contact | Andrew M. Greene, Dechao Guo, Veeraraghavan S. Basker, Robert R. Robison, Ardasheir Rahman | 2020-11-17 |
| 10833019 | Dual metal-insulator-semiconductor contact structure and formulation method | Takashi Ando, Hiroaki Niimi | 2020-11-10 |
| 10833081 | Forming isolated contacts in a stacked vertical transport field effect transistor (VTFET) | Chen Zhang, Heng Wu, Joshua M. Rubin | 2020-11-10 |
| 10833069 | Logic gate designs for 3D monolithic direct stacked VTFET | Chen Zhang, Terence B. Hook | 2020-11-10 |
| 10833079 | Dual transport orientation for stacked vertical transport field-effect transistors | Chen Zhang, Kangguo Cheng, Heng Wu | 2020-11-10 |
| 10818599 | Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts | Hiroaki Niimi, Shariq Siddiqui | 2020-10-27 |
| 10818776 | Nanosheet transistor with optimized junction and cladding detectivity control | Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Chun-Chen Yeh | 2020-10-27 |
| 10811322 | Different gate widths for upper and lower transistors in a stacked vertical transport field-effect transistor structure | Heng Wu, Kangguo Cheng, Chen Zhang | 2020-10-20 |
| 10804107 | Well and punch through stopper formation using conformal doping | Effendi Leobandung | 2020-10-13 |
| 10804270 | Contact formation through low-tempearature epitaxial deposition in semiconductor devices | Oleg Gluschenkov, Shogo Mochizuki, Hiroaki Niimi, Chun-Chen Yeh | 2020-10-13 |
| 10804136 | Fin structures with bottom dielectric isolation | Kangguo Cheng, Chun-Chen Yeh, Ruilong Xie | 2020-10-13 |
| 10784365 | Fin field effect transistor fabrication and devices having inverted T-shaped gate | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2020-09-22 |
| 10784357 | Fabrication of vertical field effect transistor structure with controlled gate length | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2020-09-22 |
| 10777465 | Integration of vertical-transport transistors and planar transistors | Ruilong Xie, Chun-Chen Yeh, Kangguo Cheng | 2020-09-15 |
| 10777468 | Stacked vertical field-effect transistors with sacrificial layer patterning | Chen Zhang, Kangguo Cheng, Oleg Gluschenkov | 2020-09-15 |
| 10748893 | Electrostatic discharge devices and methods of manufacture | Huiming Bu, Junjun Li, Theodorus E. Standaert | 2020-08-18 |
| 10749038 | Width adjustment of stacked nanowires | Kangguo Cheng, Xin Miao, Ruilong Xie | 2020-08-18 |