Issued Patents All Time
Showing 76–100 of 552 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10741647 | Conformal doping for punch through stopper in fin field effect transistor devices | Huiming Bu, Sivananda K. Kanakasabapathy, Fee Li Lie | 2020-08-11 |
| 10734502 | Prevention of extension narrowing in nanosheet field effect transistors | Chun Wing Yeung, Chen Zhang | 2020-08-04 |
| 10734499 | Unmerged epitaxial process for FinFET devices with aggressive fin pitch scaling | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie | 2020-08-04 |
| 10734477 | FinFET with reduced parasitic capacitance | Kangguo Cheng, Darsen D. Lu, Xin Miao | 2020-08-04 |
| 10714470 | Method and apparatus of forming high voltage varactor and vertical transistor on a substrate | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2020-07-14 |
| 10700209 | Independent gate FinFET with backside gate contact | Terence B. Hook, Joshua M. Rubin | 2020-06-30 |
| 10692868 | Contact formation through low-temperature epitaxial deposition in semiconductor devices | Oleg Gluschenkov, Shogo Mochizuki, Hiroaki Niimi, Chun-Chen Yeh | 2020-06-23 |
| 10692768 | Vertical transport field-effect transistor architecture | Joshua M. Rubin, Chen Zhang, Oleg Gluschenkov | 2020-06-23 |
| 10685961 | Contact formation in semiconductor devices | Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Joseph S. Washington | 2020-06-16 |
| 10680082 | Vertical FET process with controlled gate length and self-aligned junctions | Chen Zhang | 2020-06-09 |
| 10680081 | Vertical transistors with improved top source/drain junctions | Kangguo Cheng, Muthumanickam Sankarapandian, Ruilong Xie, Chun-Chen Yeh | 2020-06-09 |
| 10680064 | Techniques for VFET top source/drain epitaxy | Kangguo Cheng, Cheng Chi, Chi-Chun Liu, Ruilong Xie, Chun-Chen Yeh | 2020-06-09 |
| 10679906 | Method of forming nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness | Kangguo Cheng, Chanro Park, Ruilong Xie | 2020-06-09 |
| 10658481 | Self-aligned gate cut in direct stacked vertical transport field effect transistor (VTFET) | Chen Zhang, Kangguo Cheng, Xin Miao | 2020-05-19 |
| 10658246 | Self-aligned vertical fin field effect transistor with replacement gate structure | Chen Zhang, Kangguo Cheng, Xin Miao, Juntao Li | 2020-05-19 |
| 10643894 | Surface area and Schottky barrier height engineering for contact trench epitaxy | Jody A. Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark V. Raymond | 2020-05-05 |
| 10643893 | Surface area and Schottky barrier height engineering for contact trench epitaxy | Jody A. Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark V. Raymond | 2020-05-05 |
| 10629709 | Punch through stopper in bulk finFET device | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2020-04-21 |
| 10629680 | Sidewall image transfer nanosheet | Effendi Leobandung | 2020-04-21 |
| 10622475 | Uniform bottom spacer for VFET devices | Steven R. Bentley, Cheng Chi, Chanro Park, Ruilong Xie | 2020-04-14 |
| 10615277 | VFET CMOS dual epitaxy integration | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2020-04-07 |
| 10615255 | Fin formation for semiconductor device | Susan S. Fan, Dongseok Lee, David Moreau | 2020-04-07 |
| 10608080 | Bulk to silicon on insulator device | Terence B. Hook, Joshua M. Rubin | 2020-03-31 |
| 10607838 | Well and punch through stopper formation using conformal doping | Effendi Leobandung | 2020-03-31 |
| 10600887 | Approach to high-k dielectric feature uniformity | Chun Wing Yeung, Chen Zhang | 2020-03-24 |