Issued Patents All Time
Showing 301–325 of 552 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9806155 | Split fin field effect transistor enabling back bias on fin type field effect transistors | Veeraraghavan S. Basker, Zuoguang Liu, Xin Miao | 2017-10-31 |
| 9805973 | Dual silicide liner flow for enabling low contact resistance | Praneet Adusumilli, Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2017-10-31 |
| 9799746 | Preventing leakage inside air-gap spacer during contact formation | Kangguo Cheng, Ruilong Xie | 2017-10-24 |
| 9793157 | Etch stop for airgap protection | Kangguo Cheng, Ruilong Xie | 2017-10-17 |
| 9786737 | FinFET with reduced parasitic capacitance | Kangguo Cheng, Darsen D. Lu, Xin Miao | 2017-10-10 |
| 9786546 | Bulk to silicon on insulator device | Terence B. Hook, Joshua M. Rubin | 2017-10-10 |
| 9780185 | Spacer chamfering gate stack scheme | Hyun-Jin Cho, Hui Zang | 2017-10-03 |
| 9773881 | Etch stop for airgap protection | Kangguo Cheng, Ruilong Xie | 2017-09-26 |
| 9773709 | Forming CMOSFET structures with different contact liners | Kangguo Cheng, Zuoguang Liu | 2017-09-26 |
| 9768027 | FinFET having controlled dielectric region height | Dechao Guo, Zuoguang Liu, Chun-Chen Yeh | 2017-09-19 |
| 9768272 | Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity | Pouya Hashemi, Hong He, Alexander Reznicek | 2017-09-19 |
| 9761721 | Field effect transistors with self-aligned extension portions of epitaxial active regions | Effendi Leobandung | 2017-09-12 |
| 9761498 | Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs | Bruce B. Doris, Alexander Reznicek, Joshua M. Rubin | 2017-09-12 |
| 9741813 | Pure boron for silicide contact | Chia-Yu Chen, Zuoguang Liu, Sanjay C. Mehta | 2017-08-22 |
| 9741716 | Forming vertical and horizontal field effect transistors on the same substrate | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2017-08-22 |
| 9735248 | Pure boron for silicide contact | Chia-Yu Chen, Zuoguang Liu, Sanjay C. Mehta | 2017-08-15 |
| 9735111 | Dual metal-insulator-semiconductor contact structure and formulation method | Takashi Ando, Hiroaki Niimi | 2017-08-15 |
| 9728537 | Dual fin integration for electron and hole mobility enhancement | Chia-Yu Chen, Zuoguang Liu, Miaomiao Wang | 2017-08-08 |
| 9728624 | Semiconductor testing devices | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2017-08-08 |
| 9728462 | Stable multiple threshold voltage devices on replacement metal gate CMOS devices | Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok | 2017-08-08 |
| 9722022 | Sidewall image transfer nanosheet | Effendi Leobandung | 2017-08-01 |
| 9716160 | Extended contact area using undercut silicide extensions | Effendi Leobandung, Soon-Cheon Seo, Chun-Chen Yeh | 2017-07-25 |
| 9716170 | Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2017-07-25 |
| 9711501 | Interlayer via | Veeraraghavan S. Basker, Lawrence A. Clevenger, Terence B. Hook, Joshua M. Rubin | 2017-07-18 |
| 9711645 | Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2017-07-18 |