Issued Patents All Time
Showing 326–350 of 552 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9711618 | Fabrication of vertical field effect transistor structure with controlled gate length | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2017-07-18 |
| 9704848 | Electrostatic discharge devices and methods of manufacture | Huiming Bu, Junjun Li, Theodorus E. Standaert | 2017-07-11 |
| 9704867 | Dual fin integration for electron and hole mobility enhancement | Chia-Yu Chen, Zuoguang Liu, Miaomiao Wang | 2017-07-11 |
| 9698225 | Localized and self-aligned punch through stopper doping for finFET | Effendi Leobandung | 2017-07-04 |
| 9698061 | Polysilicon resistor formation in silicon-on-insulator replacement metal gate finFET processes | Veeraraghavan S. Basker, Huiming Bu | 2017-07-04 |
| 9698230 | MOSFET with asymmetric self-aligned contact | Kangguo Cheng, Xin Miao, Ruilong Xie | 2017-07-04 |
| 9691715 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Isaac Lauer, Jeffrey W. Sleight | 2017-06-27 |
| 9691763 | Multi-gate FinFET semiconductor device with flexible design width | Veeraraghavan S. Basker, Chun-Chen Yeh | 2017-06-27 |
| 9685537 | Gate length control for vertical transistors and integration with replacement gate flow | Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh | 2017-06-20 |
| 9680020 | Increased contact area for FinFETs | Veeraraghavan S. Basker, Chung-Hsun Lin, Zuoguang Liu, Chun-Chen Yeh | 2017-06-13 |
| 9673056 | Method to improve finFET cut overlay | Effendi Leobandung | 2017-06-06 |
| 9666726 | Localized fin width scaling using a hydrogen anneal | Veeraraghavan S. Basker, Shogo Mochizuki, Chun-Chen Yeh | 2017-05-30 |
| 9660035 | Semiconductor device including superlattice SiGe/Si fin structure | Veeraraghavan S. Basker, Chun-Chen Yeh | 2017-05-23 |
| 9659785 | Fin cut for taper device | Kangguo Cheng, Ruilong Xie | 2017-05-23 |
| 9659931 | Fin cut on sit level | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2017-05-23 |
| 9646969 | Spacer chamfering gate stack scheme | Hyun-Jin Cho, Hui Zang | 2017-05-09 |
| 9647062 | Silicon nanowire formation in replacement metal gate process | Chia-Yu Chen, Zuoguang Liu | 2017-05-09 |
| 9647093 | Fin cut for taper device | Kangguo Cheng, Ruilong Xie | 2017-05-09 |
| 9640442 | CMOS fin integration on SOI substrate | Effendi Leobandung | 2017-05-02 |
| 9640436 | MOSFET with asymmetric self-aligned contact | Kangguo Cheng, Xin Miao, Ruilong Xie | 2017-05-02 |
| 9634113 | Fully silicided linerless middle-of-line (MOL) contact | Joshua M. Rubin | 2017-04-25 |
| 9634010 | Field effect transistor device spacers | Rama Kambhampati, Junli Wang, Ruilong Xie | 2017-04-25 |
| 9634004 | Forming reliable contacts on tight semiconductor pitch | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie | 2017-04-25 |
| 9627330 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Isaac Lauer, Jeffrey W. Sleight | 2017-04-18 |
| 9620644 | Composite spacer enabling uniform doping in recessed fin devices | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2017-04-11 |