TY

Tenko Yamashita

IBM: 492 patents #21 of 70,183Top 1%
Globalfoundries: 118 patents #11 of 4,424Top 1%
TE Tessera: 5 patents #92 of 271Top 35%
CEA: 4 patents #1,058 of 7,956Top 15%
SO Sony: 4 patents #8,966 of 25,231Top 40%
ET Elpis Technologies: 3 patents #8 of 121Top 7%
RE Renesas Electronics: 3 patents #1,322 of 4,529Top 30%
AS Adeia Semiconductor Solutions: 2 patents #9 of 57Top 20%
SS Stmicroelectronics Sa: 2 patents #601 of 1,676Top 40%
KT Kabushiki Kaisha Toshiba: 1 patents #13,537 of 21,451Top 65%
SF SUNY Research Foundation: 1 patents #469 of 1,165Top 45%
Samsung: 1 patents #49,284 of 75,807Top 70%
📍 Schenectady, NY: #2 of 1,353 inventorsTop 1%
🗺 New York: #20 of 115,490 inventorsTop 1%
Overall (All Time): #309 of 4,157,543Top 1%
552
Patents All Time

Issued Patents All Time

Showing 351–375 of 552 patents

Patent #TitleCo-InventorsDate
9613958 Spacer chamfering gate stack scheme Hyun-Jin Cho, Hui Zang 2017-04-04
9607900 Method and structure to fabricate closely packed hybrid nanowires at scaled pitch Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh 2017-03-28
9608099 Nanowire semiconductor device Wilfried Haensch, Effendi Leobandung 2017-03-28
9608069 Self aligned epitaxial based punch through control Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh 2017-03-28
9607903 Method for forming field effect transistors Rama Kambhampati, Junli Wang, Ruilong Xie 2017-03-28
9601621 Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh 2017-03-21
9595597 Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh 2017-03-14
9595599 Dielectric isolated SiGe fin on bulk substrate Huiming Bu, Shogo Mochizuki 2017-03-14
9595578 Undercut insulating regions for silicon-on-insulator device Kangguo Cheng, Bruce B. Doris, Balasubramanian Pranatharthiharan, Shom Ponoth, Theodorus E. Standaert 2017-03-14
9589833 Preventing leakage inside air-gap spacer during contact formation Kangguo Cheng, Ruilong Xie 2017-03-07
9589851 Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs Huiming Bu, Hui-feng Li, Vijay Narayanan, Hiroaki Niimi 2017-03-07
9583563 Conformal doping for punch through stopper in fin field effect transistor devices Huiming Bu, Sivananda K. Kanakasabapathy, Fee Li Lie 2017-02-28
9577096 Salicide formation on replacement metal gate finFet devices Effendi Leobandung, Soon-Cheon Seo, Chun-Chen Yeh 2017-02-21
9576956 Method and structure of forming controllable unmerged epitaxial material Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie 2017-02-21
9570590 Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs Bruce B. Doris, Alexander Reznicek, Joshua M. Rubin 2017-02-14
9570554 Robust gate spacer for semiconductor devices Effendi Leobandung 2017-02-14
9564440 Spacer chamfering gate stack scheme Hyun-Jin Cho, Hui Zang 2017-02-07
9564358 Forming reliable contacts on tight semiconductor pitch Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie 2017-02-07
9558991 Formation of isolation surrounding well implantation Kangguo Cheng, Shom Ponoth, Theodorus E. Standaert 2017-01-31
9559191 Punch through stopper in bulk finFET device Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh 2017-01-31
9552988 Tone inverted directed self-assembly (DSA) fin patterning Hong He, Chi-Chun Liu, Alexander Reznicek, Chiahsun Tseng 2017-01-24
9548388 Forming field effect transistor device spacers Rama Kambhampati, Junli Wang, Ruilong Xie 2017-01-17
9548379 Asymmetric multi-gate FinFET Veeraraghavan S. Basker, Andres Bryant, Huiming Bu, Sivananda K. Kanakasabapathy 2017-01-17
9548306 Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect transistors having symmetric source/drain junctions and optional dual silicides Veeraraghavan S. Basker, Andres Bryant 2017-01-17
9548250 Semiconductor device including self-aligned gate structure and improved gate spacer topography Veeraraghavan S. Basker 2017-01-17