Issued Patents All Time
Showing 76–100 of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8299567 | Structure of metal e-fuse | Ping-Chuan Wang, Chunyan E. Tian, Wai-Kin Li | 2012-10-30 |
| 8298948 | Capping of copper interconnect lines in integrated circuit devices | Griselda Bonilla, Kaushik Chanda, Stephan Grunow, David L. Rath, Sujatha Sankaran +3 more | 2012-10-30 |
| 8237283 | Structure and method of reducing electromigration cracking and extrusion effects in semiconductor devices | Kaushik Chandra, Wai-Lin Li, Ping-Chuan Wang, Chih-Chao Yang | 2012-08-07 |
| 8237286 | Integrated circuit interconnect structure | Hanyi Ding, Jong-Ru Guo, Ping-Chuan Wang | 2012-08-07 |
| 8232646 | Interconnect structure for integrated circuits having enhanced electromigration resistance | Griselda Bonilla, Kaushik Chanda, Stephan Grunow, Chao-Kun Hu, Naftali E. Lustig +2 more | 2012-07-31 |
| 8164190 | Structure of power grid for semiconductor devices and method of making the same | Wai-Kin Li, Ping-Chuan Wang | 2012-04-24 |
| 8056039 | Interconnect structure for integrated circuits having improved electromigration characteristics | Kaushik Chanda, Stephan Grunow, Chao-Kun Hu, Sujatha Sankaran, Andrew H. Simon +1 more | 2011-11-08 |
| 8003474 | Electrically programmable fuse and fabrication method | Kaushik Chanda, Joseph M. Lukaitis, Ping-Chuan Wang | 2011-08-23 |
| 7776737 | Reliability of wide interconnects | Griselda Bonilla, Kaushik Chanda, Stephan Grunow, Sujatha Sankaran, Andrew H. Simon +1 more | 2010-08-17 |
| 7737528 | Structure and method of forming electrically blown metal fuses for integrated circuits | Griselda Bonilla, Kaushik Chanda, Jeffrey P. Gambino, Stephan Grunow, Chao-Kun Hu +3 more | 2010-06-15 |
| 7732924 | Semiconductor wiring structures including dielectric cap within metal cap layer | Kaushik Chanda, Ping-Chuan Wang, Chih-Chao Yang | 2010-06-08 |
| 7692439 | Structure for modeling stress-induced degradation of conductive interconnects | Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Jason P. Gill +7 more | 2010-04-06 |
| 7683651 | Test structure for electromigration analysis and related method | Kaushik Chanda, Ping-Chuan Wang | 2010-03-23 |
| 7683644 | Extrusion failure monitor structures | James Lloyd | 2010-03-23 |
| 7671362 | Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing | Tibor Bolom, Kaushik Chanda, Stephan Grunow, Paul S. McLaughlin, Sujatha Sankaran +3 more | 2010-03-02 |
| 7639032 | Structure for monitoring stress-induced degradation of conductive interconnects | Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Jason P. Gill +7 more | 2009-12-29 |
| 7560375 | Gas dielectric structure forming methods | Roy Iggulden, Edward W. Kiewra, Ping-Chuan Wang | 2009-07-14 |
| 7521952 | Test structure for electromigration analysis and related method | Kaushik Chanda, Ping-Chuan Wang | 2009-04-21 |
| 7473636 | Method to improve time dependent dielectric breakdown | Kaushik Chanda, James J. Demarest, Roy Iggulden, Edward W. Kiewra, Vincent J. McGahay +2 more | 2009-01-06 |
| 7397260 | Structure and method for monitoring stress-induced degradation of conductive interconnects | Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Jason P. Gill +7 more | 2008-07-08 |
| 7388224 | Structure for determining thermal cycle reliability | Jason P. Gill, Vincent J. McGahay, Paul S. McLaughlin, Conal E. Murray, Hazara S. Rathore +2 more | 2008-06-17 |
| 7361584 | Detection of residual liner materials after polishing in damascene process | Roy Iggulden, Edward W. Kiewra, Stephen K. Loh, Ping-Chuan Wang | 2008-04-22 |
| 7345305 | Control of liner thickness for improving thermal cycle reliability | Lynne M. Gignac, Vincent J. McGahay, Conal E. Murray, Hazara S. Rathore, Thomas M. Shaw +1 more | 2008-03-18 |
| 7287325 | Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing | Kaushik Chanda, James J. Demarest, Roy Iggulden, Edward W. Kiewra, Ping-Chuan Wang +1 more | 2007-10-30 |
| 7260810 | Method of extracting properties of back end of line (BEOL) chip architecture | Giovanni Fiorenza, Xiao Hu Liu, Conal E. Murray, Gregory A. Northrop, Thomas M. Shaw +2 more | 2007-08-21 |