Issued Patents All Time
Showing 26–50 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9075965 | Execution-based license discovery and optimization | Han Chen, Liangzhao Zeng, Zhe Zhang | 2015-07-07 |
| 9064727 | Sputter and surface modification etch processing for metal patterning in integrated circuits | Cyril Cabral, Jr., Benjamin L. Fletcher, Eric A. Joseph, Hiroyuki Miyazoe | 2015-06-23 |
| 9018090 | Borderless self-aligned metal contact patterning using printable dielectric materials | Josephine B. Chang, Sebastian U. Engelmann, Michael A. Guillorn, Eric A. Joseph, Adam M. Pyzyna | 2015-04-28 |
| 9006108 | Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors | Steve Koester, Isaac Lauer, Ying Zhang | 2015-04-14 |
| 8928124 | High aspect ratio and reduced undercut trench etch process for a semiconductor substrate | Eric A. Joseph, Edmund M. Sikorski, Goh Matsuura | 2015-01-06 |
| 8916054 | High fidelity patterning employing a fluorohydrocarbon-containing polymer | Markus Brink, Sebastian U. Engelmann, Michael A. Guillorn, Hiroyuki Miyazoe, Masahiro Nakamura | 2014-12-23 |
| 8871107 | Subtractive plasma etching of a blanket layer of metal or metal alloy | Eric A. Joseph, Hiroyuki Miyazoe, Mark Hoinkis, Chun Yan | 2014-10-28 |
| 8865502 | Solar cells with plated back side surface field and back side electrical contact and method of fabricating same | Kathryn C. Fisher, Satyavolu S. Papa Rao, Xiaoyan Shao, Jeffrey Hedrick | 2014-10-21 |
| 8768338 | Base station power control in a mobile network | Yasunao Katayama, Arun Natarajan | 2014-07-01 |
| 8765613 | High selectivity nitride etch process | Josephine B. Chang, Sebastian U. Engelmann, Michael A. Guillorn, Masahiro Nakamura | 2014-07-01 |
| 8768337 | Base station power control in a mobile network | Yasunao Katayama, Arun Natarajan | 2014-07-01 |
| 8754530 | Self-aligned borderless contacts for high density electronic and memory device integration | Katherina Babich, Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Michael J. Rooks | 2014-06-17 |
| 8716798 | Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors | Steve Koester, Isaac Lauer, Ying Zhang | 2014-05-06 |
| 8652969 | High aspect ratio and reduced undercut trench etch process for a semiconductor substrate | Eric A. Joseph, Edmund M. Sikorski, Goh Matsuura | 2014-02-18 |
| 8633117 | Sputter and surface modification etch processing for metal patterning in integrated circuits | Cyril Cabral, Jr., Benjamin L. Fletcher, Eric A. Joseph, Hiroyuki Miyazoe | 2014-01-21 |
| 8618036 | Aqueous cerium-containing solution having an extended bath lifetime for removing mask material | Ali Afzali-Ardakani, John A. Fitzsimmons, Mahmoud Khojasteh, Jennifer V. Muncy, George G. Totir +4 more | 2013-12-31 |
| 8455366 | Use of an organic planarizing mask for cutting a plurality of gate lines | Pratik P. Joshi, Mahmoud Khojasteh, Rajiv Ranade, George G. Totir | 2013-06-04 |
| 8445948 | Gate patterning of nano-channel devices | Sarunya Bangsaruntip, Guy M. Cohen, Sebastian U. Engelmann, Lidija Sekaric, Qingyun Yang +1 more | 2013-05-21 |
| 8431995 | Methodology for fabricating isotropically recessed drain regions of CMOS transistors | Steve Koester, Isaac Lauer, Ying Zhang | 2013-04-30 |
| 8367556 | Use of an organic planarizing mask for cutting a plurality of gate lines | Pratik P. Joshi, Mahmoud Khojasteh, Rajiv Ranade, George G. Totir | 2013-02-05 |
| 8334090 | Mixed lithography with dual resist and a single pattern transfer | Michael A. Guillorn, Balasubramanian S. Pranatharthi Haran, Jyotica V. Patel | 2012-12-18 |
| 8232171 | Structure with isotropic silicon recess profile in nanoscale dimensions | Sebastian U. Engelmann, Eric A. Joseph, Isaac Lauer, Ryan M. Martin, James Vichiconti +1 more | 2012-07-31 |
| 8159042 | Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application | Chih-Chao Yang, Lawrence A. Clevenger, Timothy J. Dalton, Louis C. Hsu | 2012-04-17 |
| 8084825 | Trilayer resist scheme for gate etching applications | Timothy J. Dalton, Ying Zhang | 2011-12-27 |
| 8049335 | System and method for plasma induced modification and improvement of critical dimension uniformity | Timothy J. Dalton, Ronald Della Guardia | 2011-11-01 |