Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
KC

Kisik Choi

IBM: 76 patents #914 of 70,183Top 2%
Globalfoundries: 42 patents #54 of 4,424Top 2%
INIntermolecular: 1 patents #186 of 248Top 75%
SESematech: 1 patents #38 of 123Top 35%
SSStmicroelectronics Sa: 1 patents #938 of 1,676Top 60%
Watervliet, NY: #3 of 109 inventorsTop 3%
New York: #547 of 115,490 inventorsTop 1%
Overall (All Time): #14,429 of 4,157,543Top 1%
100 Patents All Time

Issued Patents All Time

Showing 26–50 of 100 patents

Patent #TitleCo-InventorsDate
11600565 Top via stack Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Robert R. Robison 2023-03-07
11437317 Single-mask alternating line deposition Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Robert R. Robison 2022-09-06
11430735 Barrier removal for conductor in top via integration scheme Brent A. Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Lawrence A. Clevenger, Robert R. Robison 2022-08-30
11315872 Self-aligned top via Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang 2022-04-26
11309383 Quad-layer high-k for metal-insulator-metal capacitors Takashi Ando, Paul C. Jamison, John G. Massey, Eduard A. Cartier 2022-04-19
11302575 Subtractive line with damascene second line type Brent A. Anderson, Christopher J. Penny, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Robert R. Robison 2022-04-12
11295978 Interconnects having spacers for improved top via critical dimension and overlay tolerance Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison 2022-04-05
11289371 Top vias with selectively retained etch stops Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Robert R. Robison 2022-03-29
11276639 Conductive lines with subtractive cuts Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison 2022-03-15
11276611 Top via on subtractively etched conductive line Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison 2022-03-15
11232977 Stepped top via for via resistance reduction Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Robert R. Robison 2022-01-25
11195753 Tiered-profile contact for semiconductor Kangguo Cheng 2021-12-07
11195795 Well-controlled edge-to-edge spacing between adjacent interconnects Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison 2021-12-07
11195792 Top via stack Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Robert R. Robison 2021-12-07
11189568 Top via interconnect having a line with a reduced bottom dimension Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison 2021-11-30
11177166 Etch stop layer removal for capacitance reduction in damascene top via integration Christopher J. Penny, Brent A. Anderson, Lawrence A. Clevenger, Robert R. Robison, Nicholas Anthony Lanzillo 2021-11-16
11171084 Top via with next level line selective growth Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Robert R. Robison 2021-11-09
11164777 Top via with damascene line and via Lawrence A. Clevenger, Brent A. Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison 2021-11-02
11164815 Bottom barrier free interconnects without voids Kenneth Chun Kuen Cheng, Koichi Motoyama, Cornelius Brown Peethala, Hosadurga Shobha, Joe Lee 2021-11-02
11158537 Top vias with subtractive line formation Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison 2021-10-26
11081388 Forming barrierless contact Koichi Motoyama, Ashim Dutta, Iqbal Rashid Saraf, Benjamin D. Briggs 2021-08-03
10943990 Gate contact over active enabled by alternative spacer scheme and claw-shaped cap Andrew M. Greene, Victor Chan, Gangadhara Raja Muthinti, Veeraraghavan S. Basker, Junli Wang +1 more 2021-03-09
10892195 Method and structure for forming a vertical field-effect transistor using a replacement metal gate process Choonghyun Lee, Kangguo Cheng 2021-01-12
10886183 Method and structure for forming a vertical field-effect transistor using a replacement metal gate process Choonghyun Lee, Kangguo Cheng 2021-01-05
10748812 Air-gap containing metal interconnects Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang 2020-08-18