Issued Patents All Time
Showing 551–575 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10832955 | Methods and structures for forming uniform fins when using hardmask patterns | Peng Xu, Yann Mignot, Choonghyun Lee | 2020-11-10 |
| 10832963 | Forming gate contact over active free of metal recess | Chih-Chao Yang | 2020-11-10 |
| 10832970 | Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor | Choonghyun Lee, Juntao Li, Peng Xu | 2020-11-10 |
| 10832973 | Stress modulation of nFET and pFET fin structures | Huimei Zhou, Michael P. Belyansky, Oleg Gluschenkov, Richard A. Conti, James J. Kelly +1 more | 2020-11-10 |
| 10833165 | Asymmetric air spacer gate-controlled device with reduced parasitic capacitance | Juntao Li, Son V. Nguyen, Chanro Park | 2020-11-10 |
| 10832975 | Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement | Ruqiang Bao, Brent A. Anderson, Junli Wang, Choonghyun Lee, Hemanth Jagannathan | 2020-11-10 |
| 10833073 | Vertical transistors with different gate lengths | Xin Miao, Chen Zhang, Juntao Li | 2020-11-10 |
| 10833158 | III-V segmented finFET free of wafer bonding | Xin Miao, Chen Zhang, Wenyu Xu | 2020-11-10 |
| 10833175 | Formation of dislocation-free SiGe finFET using porous silicon | Stephen W. Bedell, Jeehwan Kim, Alexander Reznicek, Devendra K. Sadana | 2020-11-10 |
| 10833157 | iFinFET | Juntao Li, Chen Zhang, Xin Miao | 2020-11-10 |
| 10833176 | Selectively formed gate sidewall spacer | Xin Miao, Wenyu Xu, Chen Zhang | 2020-11-10 |
| 10832956 | Method and structure for forming transistors with high aspect ratio gate without patterning collapse | — | 2020-11-10 |
| 10833191 | Integrating nanosheet transistors, on-chip embedded memory, and extended-gate transistors on the same substrate | Julien Frougier, Ruilong Xie, Juntao Li | 2020-11-10 |
| 10832962 | Formation of an air gap spacer using sacrificial spacer layer | Peng Xu, Choonghyun Lee | 2020-11-10 |
| 10833079 | Dual transport orientation for stacked vertical transport field-effect transistors | Tenko Yamashita, Chen Zhang, Heng Wu | 2020-11-10 |
| 10833147 | Metal-insulator-metal capacitor structure | Veeraraghavan S. Basker, Theodoras E. Standaert, Junli Wang | 2020-11-10 |
| 10833190 | Super long channel device within VFET architecture | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2020-11-10 |
| 10833200 | Techniques for forming vertical transport FET having gate stacks with a combination of work function metals | Choonghyun Lee, Juntao Li | 2020-11-10 |
| 10832127 | Three-dimensional integration of neurosynaptic chips | Qing Cao, Zhengwen Li, Fei Liu | 2020-11-10 |
| 10833149 | Capacitors | Veeraraghavan S. Basker, Christopher J. Penny, Theodorus E. Standaert, Junli Wang | 2020-11-10 |
| 10825891 | Metal-insulator-metal capacitor structure | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2020-11-03 |
| 10825917 | Bulk FinFET with fin channel height uniformity and isolation | — | 2020-11-03 |
| 10825689 | Method of fabricating semiconductor fins by enhancing oxidation of sacrificial mandrels sidewalls through angled ion beam exposure | — | 2020-11-03 |
| 10825890 | Metal-insulator-metal capacitor structure | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2020-11-03 |
| 10818668 | Metal trench capacitor and improved isolation and methods of manufacture | Roger A. Booth, Jr., Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang | 2020-10-27 |