Issued Patents All Time
Showing 576–600 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10818756 | Vertical transport FET having multiple threshold voltages with zero-thickness variation of work function metal | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2020-10-27 |
| 10818663 | Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition | Fee Li Lie, Eric R. Miller, Sean Teehan | 2020-10-27 |
| 10818776 | Nanosheet transistor with optimized junction and cladding detectivity control | Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2020-10-27 |
| 10818559 | Formation of multi-segment channel transistor devices | — | 2020-10-27 |
| 10818791 | Nanosheet transistor with stable structure | — | 2020-10-27 |
| 10811322 | Different gate widths for upper and lower transistors in a stacked vertical transport field-effect transistor structure | Heng Wu, Chen Zhang, Tenko Yamashita | 2020-10-20 |
| 10811495 | Vertical field effect transistor with uniform gate length | Xin Miao, Wenyu Xu, Chen Zhang | 2020-10-20 |
| 10811410 | Simultaneously fabricating a high voltage transistor and a FinFET | Ali Khakifirooz, Alexander Reznicek, Charan V. V. S. Surisetty | 2020-10-20 |
| 10804262 | Cointegration of FET devices with decoupling capacitor | Juntao Li, Yi Song | 2020-10-13 |
| 10804274 | Co-integration of non-volatile memory on gate-all-around field effect transistor | Zhenxing Bi, Zheng Xu, Dexin Kong | 2020-10-13 |
| 10804136 | Fin structures with bottom dielectric isolation | Chun-Chen Yeh, Tenko Yamashita, Ruilong Xie | 2020-10-13 |
| 10804166 | Porous silicon relaxation medium for dislocation free CMOS devices | Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2020-10-13 |
| 10796966 | Vertical FET with various gate lengths by an oxidation process | Xin Miao, Chen Zhang | 2020-10-06 |
| 10796967 | Vertical field effect transistor (FET) with controllable gate length | Xin Miao, Wenyu Xu, Chen Zhang | 2020-10-06 |
| 10790825 | Multiple programmable hardware-based on-chip password | — | 2020-09-29 |
| 10788446 | Ion-sensitive field-effect transistor with micro-pillar well to enhance sensitivity | Juntao Li, Ruilong Xie, Chanro Park | 2020-09-29 |
| 10790376 | Contact structures | Ruilong Xie, Chanro Park, Julien Frougier, Andre P. Labonte | 2020-09-29 |
| 10790379 | Vertical field effect transistor with anchor | Juntao Li, Ruilong Xie | 2020-09-29 |
| 10784364 | Nanosheet with changing SiGe pecentage for SiGe lateral recess | Xin Miao, Wenyu Xu, Chen Zhang | 2020-09-22 |
| 10784363 | Method and structure of forming finFET contact | Peng Xu | 2020-09-22 |
| 10784357 | Fabrication of vertical field effect transistor structure with controlled gate length | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2020-09-22 |
| 10784370 | Vertical transistor with uniform fin thickness | — | 2020-09-22 |
| 10784148 | Forming uniform fin height on oxide substrate | Peng Xu | 2020-09-22 |
| 10784333 | Electronic devices having spiral conductive structures | Peng Xu, Xuefeng Liu, Chi-Chun Liu, Yongan Xu | 2020-09-22 |
| 10777465 | Integration of vertical-transport transistors and planar transistors | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2020-09-15 |