Issued Patents All Time
Showing 526–550 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10886378 | Method of forming air-gap spacers and gate contact over active region and the resulting device | Ruilong Xie, Julien Frougier, Chanro Park | 2021-01-05 |
| 10886367 | Forming FinFET with reduced variability | Juntao Li, Zhenxing Bi, Dexin Kong | 2021-01-05 |
| 10886363 | Metal-insulator-metal capacitor structure | Veeraraghavan S. Basker, Theodoras E. Standaert, Junli Wang | 2021-01-05 |
| 10886284 | Anti-fuse with reduced programming voltage | Juntao Li, Chengwen Pei, Geng Wang | 2021-01-05 |
| 10886271 | Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition | Fee Li Lie, Eric R. Miller, Sean Teehan | 2021-01-05 |
| 10886183 | Method and structure for forming a vertical field-effect transistor using a replacement metal gate process | Choonghyun Lee, Kisik Choi | 2021-01-05 |
| 10886169 | Airgap formation in BEOL interconnect structure using sidewall image transfer | Ekmini Anuja De Silva, Juntao Li, Yi Song, Peng Xu | 2021-01-05 |
| 10879132 | Combination of tensilely strained n-type fin field effect transistors and compressively strained p-type fin field effect transistors | — | 2020-12-29 |
| 10872962 | Steep-switch field effect transistor with integrated bi-stable resistive system | Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh | 2020-12-22 |
| 10854753 | Uniform fin dimensions using fin cut hardmask | Peng Xu | 2020-12-01 |
| 10847639 | Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy | Juntao Li | 2020-11-24 |
| 10840351 | Transistor with airgap spacer and tight gate pitch | — | 2020-11-17 |
| 10840147 | Fin cut forming single and double diffusion breaks | Juntao Li, Junli Wang, Ruilong Xie | 2020-11-17 |
| 10840148 | One-time programmable device compatible with vertical transistor processing | Juntao Li, Ruilong Xie, Chanro Park | 2020-11-17 |
| 10840329 | Nanosheet transistor having improved bottom isolation | Ruilong Xie, Chun-Chen Yeh | 2020-11-17 |
| 10840145 | Vertical field-effect transistor devices with non-uniform thickness bottom spacers | Juntao Li, Choonghyun Lee, Shogo Mochizuki | 2020-11-17 |
| 10840349 | Formation of air gap spacers for reducing parasitic capacitance | Peng Xu, Choonghyun Lee, Heng Wu | 2020-11-17 |
| 10840381 | Nanosheet and nanowire MOSFET with sharp source/drain junction | Josephine B. Chang, Michael A. Guillorn, Xin Miao | 2020-11-17 |
| 10833073 | Vertical transistors with different gate lengths | Xin Miao, Chen Zhang, Juntao Li | 2020-11-10 |
| 10833079 | Dual transport orientation for stacked vertical transport field-effect transistors | Tenko Yamashita, Chen Zhang, Heng Wu | 2020-11-10 |
| 10833175 | Formation of dislocation-free SiGe finFET using porous silicon | Stephen W. Bedell, Jeehwan Kim, Alexander Reznicek, Devendra K. Sadana | 2020-11-10 |
| 10832975 | Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement | Ruqiang Bao, Brent A. Anderson, Junli Wang, Choonghyun Lee, Hemanth Jagannathan | 2020-11-10 |
| 10833176 | Selectively formed gate sidewall spacer | Xin Miao, Wenyu Xu, Chen Zhang | 2020-11-10 |
| 10832127 | Three-dimensional integration of neurosynaptic chips | Qing Cao, Zhengwen Li, Fei Liu | 2020-11-10 |
| 10832973 | Stress modulation of nFET and pFET fin structures | Huimei Zhou, Michael P. Belyansky, Oleg Gluschenkov, Richard A. Conti, James J. Kelly +1 more | 2020-11-10 |