Issued Patents All Time
Showing 476–500 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10930754 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2021-02-23 |
| 10930734 | Nanosheet FET bottom isolation | Ruqiang Bao, Zhenxing Bi, Zheng Xu | 2021-02-23 |
| 10930568 | Method and structure to improve overlay margin of non-self-aligned contact in metallization layer | Ruilong Xie, Chanro Park, Juntao Li | 2021-02-23 |
| 10930563 | Formation of stacked nanosheet semiconductor devices | Juntao Li, Heng Wu, Peng Xu | 2021-02-23 |
| 10930510 | Semiconductor device with improved contact resistance and via connectivity | Chanro Park, Ruilong Xie, Juntao Li | 2021-02-23 |
| 10923653 | Phase change memory with gradual resistance change | — | 2021-02-16 |
| 10923590 | Wrap-around contact for vertical field effect transistors | Chanro Park, Julien Frougier, Ruilong Xie | 2021-02-16 |
| 10923471 | Minimizing shorting between FinFET epitaxial regions | Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. V. S. Surisetty | 2021-02-16 |
| 10916660 | Vertical transistor with a body contact for back-biasing | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2021-02-09 |
| 10916657 | Tensile strain in NFET channel | Peng Xu, Juntao Li, Heng Wu | 2021-02-09 |
| 10916649 | Vertical field effect transistor with reduced external resistance | Juntao Li, Choonghyun Lee, Peng Xu | 2021-02-09 |
| 10916638 | Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance | Shogo Mochizuki, Choonghyun Lee, Juntao Li | 2021-02-09 |
| 10916633 | Silicon germanium FinFET with low gate induced drain leakage current | Shogo Mochizuki, Choonghyun Lee, Juntao Li | 2021-02-09 |
| 10916630 | Nanosheet devices with improved electrostatic integrity | Ruilong Xie, Chi-Chun Liu, Cheng Chi | 2021-02-09 |
| 10916470 | Modified dielectric fill between the contacts of field-effect transistors | Vimal Kamineni, Ruilong Xie, Adra Carr | 2021-02-09 |
| 10910494 | Method and structure for forming vertical transistors with various gate lengths | Shogo Mochizuki, Choonghyun Lee, Juntao Li | 2021-02-02 |
| 10910482 | Nanosheet with changing SiGe percentage for SiGe lateral recess | Xin Miao, Wenyu Xu, Chen Zhang | 2021-02-02 |
| 10910372 | Fin field effect transistor devices with modified spacer and gate dielectric thicknesses | Xin Miao, Wenyu Xu, Chen Zhang | 2021-02-02 |
| 10910369 | On-chip security circuit | — | 2021-02-02 |
| 10903421 | Controlling filament formation and location in a resistive random-access memory device | Dexin Kong, Juntao Li, Takashi Ando | 2021-01-26 |
| 10903369 | Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions | Ruilong Xie, Julien Frougier, Chanro Park, Edward J. Nowak, Yi Qi +1 more | 2021-01-26 |
| 10903365 | Transistors with uniform source/drain epitaxy | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2021-01-26 |
| 10903358 | Vertical fin field effect transistor with reduced gate length variations | Chen Zhang, Xin Miao, Wenyu Xu | 2021-01-26 |
| 10903339 | Vertical transport FET devices having a sacrificial doped layer | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2021-01-26 |
| 10903338 | Vertical FET with shaped spacer to reduce parasitic capacitance | Junli Wang, Theodorus E. Standaert, Veeraraghavan S. Basker | 2021-01-26 |