Issued Patents All Time
Showing 176–200 of 437 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10573521 | Gate metal patterning to avoid gate stack attack due to excessive wet etching | Alexander Reznicek, Shogo Mochizuki, Joshua M. Rubin | 2020-02-25 |
| 10566246 | Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices | Heng Wu, Kangguo Cheng, Zuoguang Liu | 2020-02-18 |
| 10566453 | Vertical transistor contact for cross-coupling in a memory cell | Brent A. Anderson, Terence B. Hook | 2020-02-18 |
| 10559572 | Vertical transistor contact for a memory cell with increased density | Brent A. Anderson, Terence B. Hook | 2020-02-11 |
| 10553716 | Formation of a bottom source-drain for vertical field-effect transistors | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Shogo Mochizuki | 2020-02-04 |
| 10541331 | Fabrication of a vertical fin field effect transistor with an asymmetric gate structure | Shogo Mochizuki | 2020-01-21 |
| 10541312 | Air-gap top spacer and self-aligned metal gate for vertical fets | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2020-01-21 |
| 10529858 | FinFET with merge-free fins | Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2020-01-07 |
| 10515859 | Extra gate device for nanosheet | Bruce B. Doris, Terence B. Hook | 2019-12-24 |
| 10516064 | Multiple width nanosheet devices | Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, John H. Zhang | 2019-12-24 |
| 10504889 | Integrating a junction field effect transistor into a vertical field effect transistor | Brent A. Anderson, Huiming Bu, Terence B. Hook, Xuefeng Liu | 2019-12-10 |
| 10497629 | Self-aligned punch through stopper liner for bulk FinFET | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-12-03 |
| 10475904 | Methods of forming merged source/drain regions on integrated circuit products | Hiroaki Niimi, Steven Bentley, Romain Lallement, Brent A. Anderson, Muthumanickam Sankarapandian | 2019-11-12 |
| 10468491 | Low resistance contact for transistors | Lawrence A. Clevenger, Kirk D. Peterson, Baozhen Li, Terry A. Spooner, John E. Sheets, II | 2019-11-05 |
| 10460990 | Semiconductor via structure with lower electrical resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner | 2019-10-29 |
| 10453934 | Vertical transport FET devices having air gap top spacer | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-10-22 |
| 10446670 | Integration of strained silicon germanium PFET device and silicon NFET device for FINFET structures | Bruce B. Doris, Hong He, Nicolas Loubet | 2019-10-15 |
| 10438850 | Semiconductor device with local connection | Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, John H. Zhang | 2019-10-08 |
| 10431495 | Semiconductor device with local connection | Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, John H. Zhang | 2019-10-01 |
| 10418280 | Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-09-17 |
| 10418462 | Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process | Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie | 2019-09-17 |
| 10411128 | Strained fin channel devices | Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, John H. Zhang | 2019-09-10 |
| 10403740 | Gate planarity for FinFET using dummy polish stop | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-09-03 |
| 10396185 | Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures | Bruce B. Doris, Hong He, Nicolas Loubet | 2019-08-27 |
| 10396069 | Approach to fabrication of an on-chip resistor with a field effect transistor | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-08-27 |