Issued Patents All Time
Showing 151–175 of 276 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7750429 | Self-aligned and extended inter-well isolation structure | Thomas W. Dyer, Zhijiong Luo | 2010-07-06 |
| 7741217 | Dual workfunction silicide diode | Xiangdong Chen | 2010-06-22 |
| 7741721 | Electrical fuses and resistors having sublithographic dimensions | Charles T. Black, Matthew E. Colburn, Timothy J. Dalton, Daniel C. Edelstein, Wai-Kin Li +1 more | 2010-06-22 |
| 7737014 | Reduction of boron diffusivity in pFETs | Frederick Buehrer, Dureseti Chidambarrao, Bruce B. Doris, Hsiang-Jen Huang | 2010-06-15 |
| 7737501 | FinFET SRAM with asymmetric gate and method of manufacture thereof | Huilong Zhu | 2010-06-15 |
| 7736966 | CMOS devices with hybrid channel orientations and method for fabricating the same | Thomas W. Dyer, Xiangdong Chen, James J. Toomey | 2010-06-15 |
| 7737500 | CMOS diodes with dual gate conductors, and methods for forming the same | David M. Onsongo, Werner Rausch | 2010-06-15 |
| 7732270 | Device having enhanced stress state and related methods | Dureseti Chidambarrao, Ying Li, Rajeev Malik, Shreesh Narasimha, Huilong Zhu | 2010-06-08 |
| 7732872 | Integration scheme for multiple metal gate work function structures | Kangguo Cheng, Michael P. Chudzik, Ramachandra Divakaruni, Geng Wang, Robert C. Wong | 2010-06-08 |
| 7727890 | High aspect ratio electroplated metal feature and method | Daniel C. Edelstein, Keith Kwong Hon Wong, Chih-Chao Yang | 2010-06-01 |
| 7728392 | SRAM device structure including same band gap transistors having gate stacks with high-K dielectrics and same work function | Robert C. Wong | 2010-06-01 |
| 7718993 | Pattern enhancement by crystallographic etching | Thomas W. Dyer, Kenneth T. Settlemyer, Jr., James J. Toomey | 2010-05-18 |
| 7709960 | Dual liner capping layer interconnect structure | Chih-Chao Yang, Keith Kwong Hon Wong | 2010-05-04 |
| 7709928 | Electromigration fuse and method of fabricating same | Deok-kee Kim | 2010-05-04 |
| 7709317 | Method to increase strain enhancement with spacerless FET and dual liner process | Siddhartha Panda | 2010-05-04 |
| 7700951 | Method and structure for forming strained Si for CMOS devices | An Steegen, Ying Zhang | 2010-04-20 |
| 7696085 | Dual damascene metal interconnect structure having a self-aligned via | Wai-Kin Li | 2010-04-13 |
| 7687395 | Contact aperture and contact via with stepped sidewall and methods for fabrication thereof | Wai-Kin Li | 2010-03-30 |
| 7678658 | Structure and method for improved SRAM interconnect | Robert C. Wong | 2010-03-16 |
| 7675137 | Electrical fuse having sublithographic cavities thereupon | Deok-kee Kim, Wai-Kin Li | 2010-03-09 |
| 7666721 | SOI substrates and SOI devices, and methods for forming the same | Thomas W. Dyer, Zhijiong Luo | 2010-02-23 |
| 7659178 | Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate | Kangguo Cheng, Louis L. Hsu, Jack A. Mandelman | 2010-02-09 |
| 7659174 | Method to enhance device performance with selective stress relief | Yong Meng Lee, Victor Chan | 2010-02-09 |
| 7635899 | Structure and method to form improved isolation in a semiconductor device | Thomas W. Dyer, William C. Wille | 2009-12-22 |
| 7635620 | Semiconductor device structure having enhanced performance FET device | Xiangdong Chen | 2009-12-22 |