Issued Patents All Time
Showing 126–150 of 276 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7868461 | Embedded interconnects, and methods for forming same | Thomas W. Dyer | 2011-01-11 |
| 7863653 | Method of enhancing hole mobility | Henry K. Utomo, Judson R. Holt | 2011-01-04 |
| 7863186 | Fully and uniformly silicided gate structure and method for forming same | Wai-Kin Li | 2011-01-04 |
| 7863646 | Dual oxide stress liner | Michael P. Belyansky, Xiangdong Chen, Thomas W. Dyer, Geng Wang | 2011-01-04 |
| 7859044 | Partially gated FINFET with gate dielectric on only one sidewall | Robert C. Wong | 2010-12-28 |
| 7851885 | Methods and systems involving electrically programmable fuses | Deok-kee Kim, Keith Kwong Hon Wong, Chih-Chao Yang | 2010-12-14 |
| 7842940 | Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost | Joel P. de Souza, Keith E. Fogel, Brian J. Greene, Devendra K. Sadana | 2010-11-30 |
| 7834387 | Metal gate compatible flash memory gate stack | Roger A. Booth, Jr., Deok-kee Kim, Xiaojun Yu | 2010-11-16 |
| 7825490 | Electrical fuse having a cavity thereupon | Deok-kee Kim, Wai-Kin Li | 2010-11-02 |
| 7816231 | Device structures including backside contacts, and methods for forming same | Thomas W. Dyer | 2010-10-19 |
| 7816219 | Field effect transistors (FETs) with multiple and/or staircase silicide | Xiangdong Chen, Sunfei Fang, Zhijiong Luo, Huilong Zhu | 2010-10-19 |
| 7808082 | Structure and method for dual surface orientations for CMOS transistors | Thomas W. Dyer, Keith Kwong Hon Wong, Chih-Chao Yang | 2010-10-05 |
| 7790558 | Method and apparatus for increase strain effect in a transistor channel | Huilong Zhu | 2010-09-07 |
| 7791109 | Metal silicide alloy local interconnect | Clement Wann | 2010-09-07 |
| 7790577 | Crackstop structures and methods of making same | Xiao Hu Liu, Chih-Chao Yang | 2010-09-07 |
| 7790540 | Structure and method to use low k stress liner to reduce parasitic capacitance | Wai-Kin Li | 2010-09-07 |
| 7790542 | CMOS devices having reduced threshold voltage variations and methods of manufacture thereof | Thomas W. Dyer | 2010-09-07 |
| 7785937 | Electrical fuse having sublithographic cavities thereupon | Deok-kee Kim, Wai-Kin Li | 2010-08-31 |
| 7786527 | Sub-lithographic gate length transistor using self-assembling polymers | Wai-Kin Li | 2010-08-31 |
| 7781847 | Device patterned with sub-lithographic features with variable widths | — | 2010-08-24 |
| 7777297 | Non-planar fuse structure including angular bend | Wai-Kin Li, Deok-kee Kim | 2010-08-17 |
| 7777296 | Nano-fuse structural arrangements having blow protection barrier spaced from and surrounding fuse link | Jack A. Mandelman | 2010-08-17 |
| 7772119 | Dual liner capping layer interconnect structure | Chih-Chao Yang, Keith Kwong Hon Wong | 2010-08-10 |
| 7767099 | Sub-lithographic interconnect patterning using self-assembling polymers | Wai-Kin Li | 2010-08-03 |
| 7749890 | Low contact resistance metal contact | Keith Kwong Hon Wong, Chih-Chao Yang | 2010-07-06 |