Issued Patents All Time
Showing 176–200 of 276 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7625790 | FinFET with sublithographic fin width | — | 2009-12-01 |
| 7612414 | Overlapped stressed liners for improved contacts | Xiangdong Chen, Jun Jung Kim, Young-Gun Ko, Jae-Eun Park | 2009-11-03 |
| 7605081 | Sub-lithographic feature patterning using self-aligned self-assembly polymers | Wai-Kin Li | 2009-10-20 |
| 7592247 | Sub-lithographic local interconnects, and methods for forming same | Jack A. Mandelman, Wai-Kin Li | 2009-09-22 |
| 7576003 | Dual liner capping layer interconnect structure and method | Chih-Chao Yang, Keith Kwong Hon Wong | 2009-08-18 |
| 7572692 | Complementary transistors having different source and drain extension spacing controlled by different spacer sizes | — | 2009-08-11 |
| 7569489 | High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching | Thomas W. Dyer | 2009-08-04 |
| 7569434 | PFETs and methods of manufacturing the same | Kangguo Cheng, Louis L. Hsu, Jack A. Mandelman | 2009-08-04 |
| 7569446 | Semiconductor structure and method of manufacture | Bruce B. Doris, Thomas W. Dyer | 2009-08-04 |
| 7569447 | Method of forming transistor structure having stressed regions of opposite types | Huilong Zhu | 2009-08-04 |
| 7566651 | Low contact resistance metal contact | Keith Kwong Hon Wong, Chih-Chao Yang | 2009-07-28 |
| 7566949 | High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching | Thomas W. Dyer | 2009-07-28 |
| 7560312 | Void formation for semiconductor junction capacitance reduction | Xiangdong Chen | 2009-07-14 |
| 7560382 | Embedded interconnects, and methods for forming same | Thomas W. Dyer | 2009-07-14 |
| 7557424 | Reversible electric fuse and antifuse structures for semiconductor devices | Keith Kwong Hon Wong, Chih-Chao Yang | 2009-07-07 |
| 7553760 | Sub-lithographic nano interconnect structures, and method for forming same | Wai-Kin Li | 2009-06-30 |
| 7550338 | Method and structure for forming strained SI for CMOS devices | An Steegen, Ying Zhang | 2009-06-23 |
| 7550351 | Structure and method for creation of a transistor | Xiangdong Chen | 2009-06-23 |
| 7545034 | Thermal energy removal structure and method | Deok-kee Kim, Wai-Kin Li | 2009-06-09 |
| 7545004 | Method and structure for forming strained devices | Eng Hua Lim | 2009-06-09 |
| 7544608 | Porous and dense hybrid interconnect structure and method of manufacture | Chih-Chao Yang, Keith Kwong Hon Wong | 2009-06-09 |
| 7531384 | Enhanced interconnect structure | Chih-Chao Yang, Mukta G. Farooq, Keith Kwong Hon Wong | 2009-05-12 |
| 7531423 | Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same | Kangguo Cheng, Louis L. Hsu, Jack A. Mandelman | 2009-05-12 |
| 7528451 | CMOS gate conductor having cross-diffusion barrier | Huilong Zhu, Thomas W. Dyer | 2009-05-05 |
| 7518191 | Silicon on insulator devices having body-tied-to-source and methods of making | Thomas W. Dyer, Jack A. Mandelman, Keith Kwong Hon Wong, Chih-Chao Yang | 2009-04-14 |