Issued Patents All Time
Showing 226–250 of 276 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7381609 | Method and structure for controlling stress in a transistor channel | Huilong Zhu | 2008-06-03 |
| 7365399 | Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost | Joel P. de Souza, Keith E. Fogel, Brian J. Greene, Devendra K. Sadana | 2008-04-29 |
| 7361539 | Dual stress liner | Xiangdong Chen | 2008-04-22 |
| 7354842 | Methods of forming conductive materials | — | 2008-04-08 |
| 7348635 | Device having enhanced stress state and related methods | Dureseti Chidambarrao, Ying Li, Rajeev Malik, Shreesh Narasimha, Huilong Zhu | 2008-03-25 |
| 7309901 | Field effect transistors (FETs) with multiple and/or staircase silicide | Xiangdong Chen, Sunfei Fang, Zhijiong Luo, Huilong Zhu | 2007-12-18 |
| 7309637 | Method to enhance device performance with selective stress relief | Yong Meng Lee, Victor Chan | 2007-12-18 |
| 7307323 | Structure to use an etch resistant liner on transistor gate structure to achieve high device performance | Hung Y. Ng | 2007-12-11 |
| 7297583 | Method of making strained channel CMOS transistors having lattice-mismatched epitaxial | Huajie Chen, Dureseti Chidambarrao, Omer Dokumaci | 2007-11-20 |
| 7291528 | Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions | Huajie Chen, Dureseti Chidambarrao, Oleg Gluschenkov, An Steegen | 2007-11-06 |
| 7285488 | Method of fabricating strained channel field effect transistor pair having underlapped dual liners | — | 2007-10-23 |
| 7282435 | Method of forming contact for dual liner product | Clement Wann, Huilong Zhu | 2007-10-16 |
| 7271442 | Transistor structure having stressed regions of opposite types underlying channel and source/drain regions | Huilong Zhu | 2007-09-18 |
| 7256081 | Structure and method to induce strain in a semiconductor device channel with stressed film under the gate | Huilong Zhu | 2007-08-14 |
| 7241696 | Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer | Larry Clevenger, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik A. Kumar +5 more | 2007-07-10 |
| 7217647 | Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern | — | 2007-05-15 |
| 7211869 | Increasing carrier mobility in NFET and PFET transistors on a common wafer | Victor Chan | 2007-05-01 |
| 7193254 | Structure and method of applying stresses to PFET and NFET transistor channels for improved performance | Victor Chan, Yong Meng Lee | 2007-03-20 |
| 7186633 | Method and structure for tungsten gate metal surface treatment while preventing oxidation | — | 2007-03-06 |
| 7129126 | Method and structure for forming strained Si for CMOS devices | An Steegen, Ying Zhang | 2006-10-31 |
| 7118999 | Method and apparatus to increase strain effect in a transistor channel | Huilong Zhu | 2006-10-10 |
| 7102233 | Structure for strained channel field effect transistor pair having underlapped dual liners | — | 2006-09-05 |
| 7101744 | Method for forming self-aligned, dual silicon nitride liner for CMOS devices | Thomas W. Dyer | 2006-09-05 |
| 7098536 | Structure for strained channel field effect transistor pair having a member and a contact via | Clement Wann, Huilong Zhu | 2006-08-29 |
| 7064027 | Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance | Hung Y. Ng | 2006-06-20 |