Issued Patents All Time
Showing 201–225 of 276 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7514339 | Method for fabricating shallow trench isolation structures using diblock copolymer patterning | Wai-Kin Li | 2009-04-07 |
| 7504336 | Methods for forming CMOS devices with intrinsically stressed metal silicide layers | Robert J. Purtell, Henry K. Utomo, Yun-Yu Wang | 2009-03-17 |
| 7491585 | Electrical fuse and method of making | Chih-Chao Yang | 2009-02-17 |
| 7485508 | Two-sided semiconductor-on-insulator structures and methods of manufacturing the same | Thomas W. Dyer | 2009-02-03 |
| 7482209 | Hybrid orientation substrate and method for fabrication of thereof | Henry K. Utomo, Judson R. Holt | 2009-01-27 |
| 7482270 | Fully and uniformly silicided gate structure and method for forming same | Wai-Kin Li | 2009-01-27 |
| 7482652 | Multiwalled carbon nanotube memory device | — | 2009-01-27 |
| 7479689 | Electronically programmable fuse having anode and link surrounded by low dielectric constant material | Deok-kee Kim, Xiangdong Chen | 2009-01-20 |
| 7470943 | High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same | — | 2008-12-30 |
| 7462915 | Method and apparatus for increase strain effect in a transistor channel | Huilong Zhu | 2008-12-09 |
| 7456450 | CMOS devices with hybrid channel orientations and method for fabricating the same | Thomas W. Dyer, Xiangdong Chen, James J. Toomey | 2008-11-25 |
| 7452758 | Process for making FinFET device with body contact and buried oxide junction isolation | Thomas W. Dyer | 2008-11-18 |
| 7442611 | Method of applying stresses to PFET and NFET transistor channels for improved performance | Victor Chan, Yong Meng Lee | 2008-10-28 |
| 7442614 | Silicon on insulator devices having body-tied-to-source and methods of making | Thomas W. Dyer, Jack A. Mandelman, Keith Kwong Hon Wong, Chih-Chao Yang | 2008-10-28 |
| 7436030 | Strained MOSFETs on separated silicon layers | Thomas W. Dyer, Wai-Kin Li | 2008-10-14 |
| 7432553 | Structure and method to optimize strain in CMOSFETs | Xiangdong Chen | 2008-10-07 |
| 7429752 | Method and structure for forming strained SI for CMOS devices | An Steegen, Ying Zhang | 2008-09-30 |
| 7407890 | Patterning sub-lithographic features with variable widths | — | 2008-08-05 |
| 7396713 | Structure and method for forming asymmetrical overlap capacitance in field effect transistors | — | 2008-07-08 |
| 7396714 | Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions | Huajie Chen, Dureseti Chidambarrao, Oleg Gluschenkov, An Steegen | 2008-07-08 |
| 7396724 | Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals | Victor Chan, Yong Meng Lee, Eng Hua Lim | 2008-07-08 |
| 7390745 | Pattern enhancement by crystallographic etching | Thomas W. Dyer, Kenneth T. Settlemyer, Jr., James J. Toomey | 2008-06-24 |
| 7388267 | Selective stress engineering for SRAM stability improvement | Xiangdong Chen, Young-Gun Ko | 2008-06-17 |
| 7385258 | Transistors having v-shape source/drain metal contacts | Huilong Zhu, Zhijiong Luo | 2008-06-10 |
| 7384852 | Sub-lithographic gate length transistor using self-assembling polymers | Wai-Kin Li | 2008-06-10 |