Issued Patents All Time
Showing 76–100 of 276 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8674444 | Structure and method of forming a transistor with asymmetric channel and source/drain regions | Kangguo Cheng, Robert C. Wong | 2014-03-18 |
| 8629506 | Replacement gate CMOS | Kangguo Cheng | 2014-01-14 |
| 8587062 | Silicon on insulator (SOI) field effect transistors (FETs) with adjacent body contacts | Jack A. Mandelman | 2013-11-19 |
| 8558320 | Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior | Chock Hing Gan, Zhongze Wang, Beom-Mo Han | 2013-10-15 |
| 8513769 | Electrical fuses and resistors having sublithographic dimensions | Charles T. Black, Matthew E. Colburn, Timothy J. Dalton, Daniel C. Edelstein, Wai-Kin Li +1 more | 2013-08-20 |
| 8497168 | Structure and method to enhance both NFET and PFET performance using different kinds of stressed layers | Bruce B. Doris, Huilong Zhu | 2013-07-30 |
| 8492871 | Electrical fuse and method of making | Chih-Chao Yang | 2013-07-23 |
| 8476717 | Semiconductor transistors having reduced distances between gate electrode regions | Robert C. Wong | 2013-07-02 |
| 8476674 | Gate conductor with a diffusion barrier | Wai-Kin Li | 2013-07-02 |
| 8461625 | Carrier mobility enhanced channel devices and method of manufacture | Kangguo Cheng | 2013-06-11 |
| 8456006 | Hybrid interconnect structure for performance improvement and reliability enhancement | Chih-Chao Yang, Thomas M. Shaw, Keith Kwong Hon Wong | 2013-06-04 |
| 8441000 | Heterojunction tunneling field effect transistors, and methods for fabricating the same | Xiangdong Chen | 2013-05-14 |
| 8432764 | Boost cell supply write assist | Omer Heymann, Dana Bar-Niv, Noam Jungmann, Elazar Kachir, Udi Nir +3 more | 2013-04-30 |
| 8405131 | High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same | — | 2013-03-26 |
| 8361704 | Method for reducing tip-to-tip spacing between lines | Matthew E. Colburn, Wai-Kin Li | 2013-01-29 |
| 8338292 | Body contacts for FET in SOI SRAM array | Yue Tan, Zhibin Ren, Richard A. Wachnik | 2012-12-25 |
| 8293631 | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing | Thomas W. Dyer | 2012-10-23 |
| 8232210 | Double patterning process for integrated circuit device manufacturing | Kangguo Cheng | 2012-07-31 |
| 8232150 | Structure and method of forming a transistor with asymmetric channel and source/drain regions | Kangguo Cheng, Robert C. Wong | 2012-07-31 |
| 8222702 | CMOS diodes with dual gate conductors, and methods for forming the same | David M. Onsongo, Werner Rausch | 2012-07-17 |
| 8217470 | Field effect device including recessed and aligned germanium containing channel | Xiangdong Chen, Brian J. Greene | 2012-07-10 |
| 8194478 | Systems and methods for writing to multiple port memory circuits | Zhongze Wang, Changho Jung | 2012-06-05 |
| 8178945 | Programmable PN anti-fuse | Ping-Chuan Wang, Robert C. Wong | 2012-05-15 |
| 8173532 | Semiconductor transistors having reduced distances between gate electrode regions | Robert C. Wong | 2012-05-08 |
| 8159031 | SOI substrates and SOI devices, and methods for forming the same | Thomas W. Dyer, Zhijiong Luo | 2012-04-17 |