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Hierarchy-aware integrated circuit layout design |
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Adaptive SRAM memory control |
Israel A. Wagner, Yevgeniy Kuklin |
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Short circuit detection in a read/write assist capacitor of a memory |
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Clock gating circuit for avoiding out-of-spec clock operations in self-timed circuits |
Israel A. Wagner, Hezi Shalom, Elazar Kachir, Tomer Cohen |
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Synchronized memory repair system (SRS) |
Yaron Freiman, Tomer Cohen, Elazar Kachir, Hezi Shalom |
2024-02-06 |
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Analysis of signal transitions in feedback circuits |
Israel A. Wagner |
2021-11-16 |
| 10825543 |
Locating failures in memory with redundancy |
Hezi Shalom, Israel A. Wagner, Yaron Freiman, Amit Amos Atias |
2020-11-03 |
| 10762953 |
Memory array with reduced circuitry |
Donald W. Plass |
2020-09-01 |
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Area-efficient dynamic capacitor circuit for noise reduction in VLSI circuits |
Israel A. Wagner, Elazar Kachir |
2020-08-25 |
| 9825619 |
Self-timed, log-space, voltage-controlled delay line |
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| 9465905 |
Structure for static random access memory |
Lior Arie, Lidar Herooti, Elazar Kachir, Hezi Shalom, Israel A. Wagner |
2016-10-11 |
| 9466358 |
Structure for static random access memory |
Lior Arie, Lidar Herooti, Elazar Kachir, Hezi Shalom, Israel A. Wagner |
2016-10-11 |
| 9343182 |
Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability |
Israel A. Wagner |
2016-05-17 |
| 9299458 |
Voltage comparator circuit and usage thereof |
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Voltage comparator circuit and usage thereof |
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2016-02-16 |
| 9099200 |
SRAM restore tracking circuit and method |
Lior Binyamini, Elazar Kachir, Donald W. Plass |
2015-08-04 |
| 8937840 |
Digital voltage boost circuit |
James Dawson, Elazar Kachir, Udi Nir, Donald W. Plass |
2015-01-20 |
| 8472271 |
Systems and methods for memory device precharging |
James Dawson, Rajiv V. Joshi, Elazar Kachir, Rouwaida N. Kanj, Ehud Nir +1 more |
2013-06-25 |
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Boost cell supply write assist |
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2013-04-30 |
