Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9059191 | Chamfered corner crackstop for an integrated circuit chip | Mark C. Lamorey | 2015-06-16 |
| 9057760 | Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structures | Luke D. LaCroix, Mark C. Lamorey, Steven F. Oakland, Janak G. Patel, Kerry P. Pfarr +1 more | 2015-06-16 |
| 9059127 | Packages for three-dimensional die stacks | Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr. | 2015-06-16 |
| 9018040 | Power distribution for 3D semiconductor package | Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr. | 2015-04-28 |
| 9006739 | Semiconductor test and monitoring structure to detect boundaries of safe effective modulus | James V. Crain, Jr., Mark C. H. Lamorey, Christopher D. Muzzy, Thomas M. Shaw | 2015-04-14 |
| 8999846 | Elongated via structures | Luke D. LaCroix, Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr. | 2015-04-07 |
| 8952503 | Organic module EMI shielding structures and methods | William L. Brodsky, Timothy W. Budell, Samuel R. Connor, Mark C. Lamorey, Janak G. Patel +1 more | 2015-02-10 |
| 8796133 | Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections | Griselda Bonilla, Timothy H. Daubenspeck, Mark C. H. Lamorey, Howard S. Landis, Xiao Hu Liu +2 more | 2014-08-05 |
| 8759977 | Elongated via structures | Luke D. LaCroix, Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr. | 2014-06-24 |
| 8756546 | Elastic modulus mapping of a chip carrier in a flip chip package | Erwin B. Cohen, Mark C. H. Lamorey, Marek A. Orlowski, Douglas O. Powell, David L. Questad +1 more | 2014-06-17 |
| 8653662 | Structure for monitoring stress induced failures in interlevel dielectric layers of solder bump integrated circuits | Luke D. LaCroix, Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr. | 2014-02-18 |
| 8586982 | Semiconductor test chip device to mimic field thermal mini-cycles to assess reliability | Luke D. LaCroix, Janak G. Patel, Peter Slota, Jr. | 2013-11-19 |
| 8294025 | Lateral collection photovoltaics | Stephen J. Fonash, Handong Li | 2012-10-23 |
| 8044512 | Electrical property altering, planar member with solder element in IC chip package | J. Richard Behun | 2011-10-25 |
| 7765509 | Auto connection assignment system and method | Adam Matthew Bittner, Timothy W. Budell, Robert Cusimano, Richard Dauphin, Matthew T. Guzowski +2 more | 2010-07-27 |
| 7560950 | Packaging reliability superchips | Jason E. Blanchet, James V. Crain, Jr., Charles W. Griffin, Robert F. White | 2009-07-14 |
| 7351917 | Vents with signal image for signal return path | Timothy W. Budell, Thomas P. Comino, Todd W. Davies, Ross W. Keesler, Steven G. Rosser | 2008-04-01 |
| 7348792 | Packaging reliability super chips | Jason E. Blanchet, James V. Crain, Jr., Charles W. Griffin, Robert F. White | 2008-03-25 |
| 7275229 | Auto connection assignment system and method | Adam Matthew Bittner, Timothy W. Budell, Robert Cusimano, Richard Dauphin, Matthew T. Guzowski +2 more | 2007-09-25 |
| 7196908 | Dual pitch contact pad footprint for flip-chip chips and modules | Timothy W. Budell, Jerzy M. Zalesinski | 2007-03-27 |
| 7102377 | Packaging reliability superchips | Jason E. Blanchet, James V. Crain, Jr., Charles W. Griffin, Robert F. White | 2006-09-05 |
| 7024764 | Method of making an electronic package | John S. Kresge, Robert David Sebesta, James R. Wilcox | 2006-04-11 |
| 6977345 | Vents with signal image for signal return path | Timothy W. Budell, Thomas P. Comino, Todd W. Davies, Ross W. Keesler, Steven G. Rosser | 2005-12-20 |
| 6829823 | Method of making a multi-layered interconnect structure | Francis J. Downes, Jr., Donald S. Farquhar, Elizabeth Foster, Robert M. Japp, Gerald W. Jones +3 more | 2004-12-14 |
| 6793500 | Radial contact pad footprint and wiring for electrical components | Timothy W. Budell, Esmaeil Rahmati, Jerzy M. Zalesinski | 2004-09-21 |