Issued Patents All Time
Showing 351–375 of 408 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6355531 | Method for fabricating semiconductor devices with different properties using maskless process | Jack A. Mandelman, Louis L. Hsu, William R. Tonti, Li-Kong Wang | 2002-03-12 |
| 6352892 | Method of making DRAM trench capacitor | Rajarao Jammy, Jack A. Mandelman | 2002-03-05 |
| 6348374 | Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure | Satish D. Athavale, Gary B. Bronner, Ramachandra Divakaruni, Ulrike Gruening, Jack A. Mandelman | 2002-02-19 |
| 6344389 | Self-aligned damascene interconnect | Gary B. Bronner, Jeffrey P. Gambino | 2002-02-05 |
| 6339241 | Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch | Jack A. Mandelman, Ramachandra Divakaruni, Ulrike Gruening | 2002-01-15 |
| 6339239 | DRAM cell layout for node capacitance enhancement | Johann Alsmeier | 2002-01-15 |
| 6319788 | Semiconductor structure and manufacturing methods | Ulrike Gruening, Martin Schrems | 2001-11-20 |
| 6320215 | Crystal-axis-aligned vertical side wall device | Gary B. Bronner, Ulrike Gruening, Jack A. Mandelman | 2001-11-20 |
| 6309924 | Method of forming self-limiting polysilicon LOCOS for DRAM cell | Ramachandra Divakaruni, Jack A. Mandelman, Irene McStay, Larry Nesbit, Helmut Tews | 2001-10-30 |
| 6297086 | Application of excimer laser anneal to DRAM processing | Suryanarayan G. Hegde, Kam-Leung Lee, Jack A. Mandelman | 2001-10-02 |
| 6288422 | Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance | Jack A. Mandelman, Rama Divakaruni | 2001-09-11 |
| 6284593 | Method for shallow trench isolated, contacted well, vertical MOSFET DRAM | Jack A. Mandelman, Ramachandra Divakaruni | 2001-09-04 |
| 6282116 | Dynamic random access memory | Gerhard Kunkel, Shahid Butt | 2001-08-28 |
| 6274467 | Dual work function gate conductors with self-aligned insulating cap | Jeffrey P. Gambino, Louis L. Hsu, Jack A. Mandelman, William R. Tonti | 2001-08-14 |
| 6271142 | Process for manufacture of trench DRAM capacitor buried plates | Ulrike Gruening, Dirk Tobben | 2001-08-07 |
| 6268638 | Metal wire fuse structure with cavity | Axel Brintzinger, Edward W. Kiewra, Chandrasekhar Narayan | 2001-07-31 |
| 6265308 | Slotted damascene lines for low resistive wiring lines for integrated circuit | Gary B. Bronner, Greg Costrini, Rainer Florian Schnabel | 2001-07-24 |
| 6265279 | Method for fabricating a trench capacitor | Jack A. Mandelman, Joachim Hoepfner | 2001-07-24 |
| 6261914 | Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer | Ramachandra Divakaruni, Jeffrey P. Gambino, Jeremy K. Stephens | 2001-07-17 |
| 6261894 | Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays | Jack A. Mandelman, Ramachandra Divakaruni | 2001-07-17 |
| 6258689 | Low resistance fill for deep trench capacitor | Gary B. Bronner, Jeffrey P. Gambino, Jack A. Mandelman, Rick L. Mohler, William R. Tonti | 2001-07-10 |
| 6259129 | Strap with intrinsically conductive barrier | Jeffrey P. Gambino, Rajarao Jammy, Jack A. Mandelman | 2001-07-10 |
| 6259135 | MOS transistors structure for reducing the size of pitch limited circuits | Louis L. Hsu | 2001-07-10 |
| 6255683 | Dynamic random access memory | Ulrike Gruening, John K. DeBrosse, Jack A. Mandelman | 2001-07-03 |
| 6255158 | Process of manufacturing a vertical dynamic random access memory device | Toshiharu Furukawa, Ulrike Gruening, David V. Horak, Jack A. Mandelman, Thomas Rupp | 2001-07-03 |