Issued Patents All Time
Showing 376–400 of 408 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6251710 | Method of making a dual damascene anti-fuse with via before wire | Axel Brintzinger | 2001-06-26 |
| 6245651 | Method of simultaneously forming a line interconnect and a borderless contact to diffusion | Rama Divakaruni, Larry Nesbit | 2001-06-12 |
| 6236077 | Trench electrode with intermediate conductive barrier layer | Jeffrey P. Gambino, Rajarao Jammy, Jack A. Mandelman | 2001-05-22 |
| 6229173 | Hybrid 5F2 cell layout for buried surface strap aligned to vertical transistor | Ulrike Gruening | 2001-05-08 |
| 6222218 | DRAM trench | Rajarao Jammy, Jack A. Mandelman | 2001-04-24 |
| 6211544 | Memory cell layout for reduced interaction between storage nodes and transistors | Young Jin Park, Gerhard Kunkel | 2001-04-03 |
| 6204140 | Dynamic random access memory | Ulrike Gruening, Jochen Beintner, Scott D. Halle, Jack A. Mandelman, Juergen Wittmann +1 more | 2001-03-20 |
| 6201272 | Method for simultaneously forming a storage-capacitor electrode and interconnect | David E. Kotecki, Jeffrey P. Gambino, Gary B. Bronner | 2001-03-13 |
| 6200834 | Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (CMP) planarization | Gary B. Bronner, Jeffrey P. Gambino | 2001-03-13 |
| 6194755 | Low-resistance salicide fill for trench capacitors | Jeffrey P. Gambino, Ulrike Gruening, Jack A. Mandelman | 2001-02-27 |
| 6194301 | Method of fabricating an integrated circuit of logic and memory using damascene gate structure | Mary E. Weybright, Gary B. Bronner | 2001-02-27 |
| 6190979 | Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill | Mary E. Weybright | 2001-02-20 |
| 6190971 | Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region | Ulrike Gruening | 2001-02-20 |
| 6184107 | Capacitor trench-top dielectric for self-aligned device isolation | Rama Divakaruni, Ulrike Gruening, Byeong Y. Kim, Jack A. Mandelman, Larry Nesbit | 2001-02-06 |
| 6180975 | Depletion strap semiconductor memory device | Mary E. Weybright | 2001-01-30 |
| 6177696 | Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices | Gary B. Bronner, Laertis Economikos, Rajarao Jammy, Byeongju Park, Martin Schrems | 2001-01-23 |
| 6174762 | Salicide device with borderless contact | Gary B. Bronner, Jeffrey P. Gambino, Louis L. Hsu, Jack A. Mandelman, William R. Tonti | 2001-01-16 |
| 6165864 | Tapered electrode for stacked capacitors | Hua Shen, Joachim Nuetzel, David E. Kotecki | 2000-12-26 |
| 6153902 | Vertical DRAM cell with wordline self-aligned to storage trench | Toshiharu Furukawa, Ulrike Gruening, David V. Horak, Jack A. Mandelman, Thomas Rupp | 2000-11-28 |
| 6150212 | Shallow trench isolation method utilizing combination of spacer and fill | Ramachandra Divakaruni, Jeffrey P. Gambino, Jack A. Mandelman, William R. Tonti | 2000-11-21 |
| 6143599 | Method for manufacturing memory cell with trench capacitor | Byeong Y. Kim, Jochen Beintner | 2000-11-07 |
| 6140175 | Self-aligned deep trench DRAM array device | Richard L. Kleinhenz | 2000-10-31 |
| 6124199 | Method for simultaneously forming a storage-capacitor electrode and interconnect | Jeffrey P. Gambino, Gary B. Bronner, David E. Kotecki | 2000-09-26 |
| 6118683 | Dynamic random access memory cell layout | Gerhard Kunkel, Shahid Butt | 2000-09-12 |
| 6110792 | Method for making DRAM capacitor strap | Gary B. Bronner, Juergen Wittmann | 2000-08-29 |