Issued Patents All Time
Showing 76–100 of 213 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10354921 | Stacked transistors with different channel widths | Kangguo Cheng, Lawrence A. Clevenger, John H. Zhang | 2019-07-16 |
| 10347633 | Spacer for trench epitaxial structures | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2019-07-09 |
| 10347749 | Reducing bending in parallel structures in semiconductor fabrication | Pietro Montanini, John R. Sporre, Ruilong Xie | 2019-07-09 |
| 10347632 | Forming spacer for trench epitaxial structures | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2019-07-09 |
| 10340189 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Junli Wang, Ruilong Xie | 2019-07-02 |
| 10325848 | Self-aligned local interconnect technology | Andrew M. Greene, Injo Ok, Charan V. V. S. Surisetty, Ruilong Xie | 2019-06-18 |
| 10304747 | Dual liner silicide | Ruilong Xie, Chun-Chen Yeh | 2019-05-28 |
| 10304741 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Junli Wang, Ruilong Xie | 2019-05-28 |
| 10297506 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Ruilong Xie | 2019-05-21 |
| 10276569 | Minimizing shorting between FinFET epitaxial regions | Kangguo Cheng, Alexander Reznicek, Charan V. Surisetty | 2019-04-30 |
| 10256296 | Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2019-04-09 |
| 10256239 | Spacer formation preventing gate bending | Eric R. Miller, Soon-Cheon Seo, John R. Sporre | 2019-04-09 |
| 10249624 | Semiconductor structure containing low-resistance source and drain contacts | Injo Ok, Charan V. Surisetty | 2019-04-02 |
| 10242981 | Fin cut during replacement gate formation | Andrew M. Greene, Sivananda K. Kanakasabapathy, John R. Sporre | 2019-03-26 |
| 10236253 | Self-aligned local interconnect technology | Andrew M. Greene, Injo Ok, Charan V. V. S. Surisetty, Ruilong Xie | 2019-03-19 |
| 10236212 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Junli Wang, Ruilong Xie | 2019-03-19 |
| 10229852 | Self-aligned low dielectric constant gate cap and a method of forming the same | Injo Ok, Charan V. Surisetty | 2019-03-12 |
| 10224326 | Fin cut during replacement gate formation | Andrew M. Greene, Sivananda K. Kanakasabapathy, John R. Sporre | 2019-03-05 |
| 10186599 | Forming self-aligned contact with spacer first | Su Chen Fan, Andrew M. Greene, Sean Lian, Mark V. Raymond, Ruilong Xie | 2019-01-22 |
| 10170498 | Strained CMOS on strain relaxation buffer substrate | Kangguo Cheng, Juntao Li | 2019-01-01 |
| 10170482 | Structure to prevent lateral epitaxial growth in semiconductor devices | Hui Zang | 2019-01-01 |
| 10141338 | Strained CMOS on strain relaxation buffer substrate | Kangguo Cheng, Juntao Li | 2018-11-27 |
| 10134760 | FinFETs with various fin height | Kangguo Cheng, Terence B. Hook, Xin Miao | 2018-11-20 |
| 10128151 | Devices and methods of cobalt fill metallization | Vimal Kamineni, James J. Kelly, Praneet Adusumilli, Oscar van der Straten | 2018-11-13 |
| 10121789 | Self-aligned source/drain contacts | Praneet Adusumilli, Emre Alptekin, Kangguo Cheng, Shom Ponoth | 2018-11-06 |