Issued Patents All Time
Showing 101–125 of 213 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10109722 | Etch-resistant spacer formation on gate structure | Ruilong Xie, Zhenxing Bi, Pietro Montanini, Eric R. Miller, Oleg Gluschenkov +2 more | 2018-10-23 |
| 10090202 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Junli Wang, Ruilong Xie | 2018-10-02 |
| 10083861 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Ruilong Xie | 2018-09-25 |
| 10074569 | Minimize middle-of-line contact line shorts | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2018-09-11 |
| 10043904 | Method and structure of improving contact resistance for passive and long channel devices | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2018-08-07 |
| 10032674 | Middle of the line subtractive self-aligned contacts | Joshua M. Rubin | 2018-07-24 |
| 10020306 | Spacer for trench epitaxial structures | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2018-07-10 |
| 10020229 | Fin type field effect transistors with different pitches and substantially uniform fin reveal | Zhenxing Bi, Kangguo Cheng, Thamarai S. Devarajan | 2018-07-10 |
| 10014295 | Self heating reduction for analog radio frequency (RF) device | Injo Ok, Charan V. Surisetty, Soon-Cheon Seo, Tenko Yamashita | 2018-07-03 |
| 10014220 | Self heating reduction for analog radio frequency (RF) device | Injo Ok, Charan V. Surisetty, Soon-Cheon Seo, Tenko Yamashita | 2018-07-03 |
| 10002792 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Ruilong Xie | 2018-06-19 |
| 9997419 | Confined eptaxial growth for continued pitch scaling | Sivananda K. Kanakasabapathy | 2018-06-12 |
| 9997418 | Dual liner silicide | Ruilong Xie, Chun-Chen Yeh | 2018-06-12 |
| 9985024 | Minimizing shorting between FinFET epitaxial regions | Kangguo Cheng, Alexander Reznicek, Charan V. Surisetty | 2018-05-29 |
| 9953976 | Effective device formation for advanced technology nodes with aggressive fin-pitch scaling | Injo Ok, Sanjay C. Mehta, Soon-Cheon Seo, Charan V. Surisetty | 2018-04-24 |
| 9935168 | Gate contact with vertical isolation from source-drain | David V. Horak, Shom Ponoth, Ruilong Xie | 2018-04-03 |
| 9935003 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Ruilong Xie | 2018-04-03 |
| 9929059 | Dual liner silicide | Ruilong Xie, Chun-Chen Yeh | 2018-03-27 |
| 9929057 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Ruilong Xie | 2018-03-27 |
| 9923078 | Trench silicide contacts with high selectivity process | Andrew M. Greene, Ruilong Xie | 2018-03-20 |
| 9911823 | POC process flow for conformal recess fill | Andrew M. Greene, Sanjay C. Mehta, Ruilong Xie | 2018-03-06 |
| 9905479 | Semiconductor devices with sidewall spacers of equal thickness | Kangguo Cheng, Soon-Cheon Seo | 2018-02-27 |
| 9905463 | Self-aligned low dielectric constant gate cap and a method of forming the same | Injo Ok, Charan V. Surisetty | 2018-02-27 |
| 9905421 | Improving channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2018-02-27 |
| 9893085 | Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2018-02-13 |