Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9735154 | Semiconductor structure having gap fill dielectric layer disposed between fins | Andy Wei, Dae-Han Choi, Dae Geun Yang, Mariappan Hariharaputhiran | 2017-08-15 |
| 9666476 | Dimension-controlled via formation processing | Yuping Ren, Duohui Bei, Sipeng Gu, Huang Liu | 2017-05-30 |
| 9520395 | FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack | Guillaume Bouche, Andy Wei, Jerome F. Wandell, Sandeep Gaan | 2016-12-13 |
| 9508794 | Mixed N/P-type fin semiconductor structure with epitaxial materials having increased surface area through multiple epitaxial heads | Xusheng Wu, Changyong Xiao, Wanxun He | 2016-11-29 |
| 9490129 | Integrated circuits having improved gate structures and methods for fabricating same | Huang Liu | 2016-11-08 |
| 9460963 | Self-aligned contacts and methods of fabrication | Gabriel Padron Wells, Guillaume Bouche, Andre P. Labonte | 2016-10-04 |
| 9431528 | Lithographic stack excluding SiARC and method of using same | Hong Yu, Zhao Lun, Huang Liu | 2016-08-30 |
| 9414258 | Method and apparatus for processing bearer | Zhiyu Di, Shaohui Hou | 2016-08-09 |
| 9401263 | Feature etching using varying supply of power pulses | Gabriel Padron Wells, Jack Chao-Hsu Chang, Mingmei Wang, Taejoon Han | 2016-07-26 |
| 9391846 | Policy formulating method, policy server, and gateway | Yusheng Hu | 2016-07-12 |
| 9305832 | Dimension-controlled via formation processing | Yuping Ren, Duohui Bei, Sipeng Gu, Huang Liu | 2016-04-05 |
| 9305785 | Semiconductor contacts and methods of fabrication | Andy Wei, Guillaume Bouche, Gabriel Padron Wells | 2016-04-05 |
| 9281249 | Decoupling measurement of layer thicknesses of a plurality of layers of a circuit structure | Alok Vaid, Abner Bello, Sipeng Gu, Lokesh Subramany, Akshey Sehgal | 2016-03-08 |
| 9275906 | Method for increasing a surface area of epitaxial structures in a mixed N/P type fin semiconductor structure by forming multiple epitaxial heads | Xusheng Wu, Changyong Xiao, Wanxun He | 2016-03-01 |
| 9236301 | Customized alleviation of stresses generated by through-substrate via(S) | Guoxiang Ning, Paul Ackmann, Sarasvathi Thangaraju | 2016-01-12 |
| 9224842 | Patterning multiple, dense features in a semiconductor device using a memorization layer | Guillaume Bouche, Andy Wei, Jerome F. Wandell, Sandeep Gaan | 2015-12-29 |
| 9196499 | Method of forming semiconductor fins | Andy Wei, Dae-Han Choi, Dae Geun Yang, Mariappan Hariharaputhiran | 2015-11-24 |
| 9129905 | Planar metrology pad adjacent a set of fins of a fin field effect transistor device | Lokesh Subramany, Alok Vaid, Sipeng Gu, Akshey Sehgal | 2015-09-08 |
| 9121890 | Planar metrology pad adjacent a set of fins of a fin field effect transistor device | Sipeng Gu, Alok Vaid, Lokesh Subramany, Akshey Sehgal | 2015-09-01 |
| 9105478 | Devices and methods of forming fins at tight fin pitches | Andy Wei, Mariappan Hariharaputhiran, Dae Geun Yang, Dae-Han Choi, Richard J. Carter +1 more | 2015-08-11 |
| 9064848 | ARC residue-free etching | Richard Wise, Habib Hichri, Catherine B. Labelle | 2015-06-23 |
| 9040380 | Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same | Jin Ping Liu, Jill C. Hildreth, Taejoon Han | 2015-05-26 |
| 9034767 | Facilitating mask pattern formation | Dae-Han Choi, Dae Geun Yang, Taejoon Han, Andy Wei | 2015-05-19 |
| 8940641 | Methods for fabricating integrated circuits with improved patterning schemes | Taejoon Han, Hui Peng Koh | 2015-01-27 |
| 8916472 | Interconnect formation using a sidewall mask layer | Mingmei Wang, Liu Huang | 2014-12-23 |