Issued Patents All Time
Showing 151–175 of 220 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7902061 | Interconnect structures with encasing cap and methods of making thereof | Lawrence A. Clevenger, Timothy J. Dalton, Louis C. Hsu, Carl Radens, Theodorus E. Standaert +1 more | 2011-03-08 |
| 7867895 | Method of fabricating improved interconnect structure with a via gouging feature absent profile damage to the interconnect dielectric | Chih-Chao Yang | 2011-01-11 |
| 7851885 | Methods and systems involving electrically programmable fuses | Deok-kee Kim, Chih-Chao Yang, Haining Yang | 2010-12-14 |
| 7851321 | Semiconductor integrated circuit devices having high-Q wafer back-side capacitors | Lawrence A. Clevenger, Timothy J. Dalton, Louis L. Hsu, Carl Radens, Vidhya Ramachandran +1 more | 2010-12-14 |
| 7838908 | Semiconductor device having dual metal gates and method of manufacture | Unoh Kwon, Siddarth A. Krishnan, Takashi Ando, Michael P. Chudzik, Martin M. Frank +5 more | 2010-11-23 |
| 7838873 | Structure for stochastic integrated circuit personalization | Lawrence A. Clevenger, Matthew E. Colburn, Timothy J. Dalton, Michael C. Gaidis, Louis L. Hsu +2 more | 2010-11-23 |
| 7825420 | Method for forming slot via bitline for MRAM devices | Michael C. Gaidis, Carl Radens, Lawrence A. Clevenger, Timothy J. Dalton, Louis L. Hsu +1 more | 2010-11-02 |
| 7808082 | Structure and method for dual surface orientations for CMOS transistors | Haining Yang, Thomas W. Dyer, Chih-Chao Yang | 2010-10-05 |
| 7772119 | Dual liner capping layer interconnect structure | Chih-Chao Yang, Haining Yang | 2010-08-10 |
| 7759741 | Method and apparatus for forming nickel silicide with low defect density in FET devices | Robert J. Purtell | 2010-07-20 |
| 7754594 | Method for tuning the threshold voltage of a metal gate and high-k device | Michael P. Chudzik, Michael A. Gribelyuk, Rashmi Jha, Renee T. Mo, Naim Moumen | 2010-07-13 |
| 7750418 | Introduction of metal impurity to change workfunction of conductive electrodes | Michael P. Chudzik, Bruce B. Doris, Supratik Guha, Rajarao Jammy, Vijay Narayanan +2 more | 2010-07-06 |
| 7749890 | Low contact resistance metal contact | Chih-Chao Yang, Haining Yang | 2010-07-06 |
| 7737026 | Structure and method for low resistance interconnections | Ying Li | 2010-06-15 |
| 7727890 | High aspect ratio electroplated metal feature and method | Daniel C. Edelstein, Chih-Chao Yang, Haining Yang | 2010-06-01 |
| 7726010 | Method of forming a micro-electromechanical (MEMS) switch | Louis C. Hsu, Lawrence A. Clevenger, Timothy J. Dalton, Carl Radens, Chih-Chao Yang | 2010-06-01 |
| 7709960 | Dual liner capping layer interconnect structure | Chih-Chao Yang, Haining Yang | 2010-05-04 |
| 7691701 | Method of forming gate stack and structure thereof | Michael P. Belyansky, Siddarth A. Krishnan, Unoh Kwon, Naim Moumen, Ravikumar Ramachandran +3 more | 2010-04-06 |
| 7659199 | Air break for improved silicide formation with composite caps | Robert J. Purtell | 2010-02-09 |
| 7635884 | Method and structure for forming slot via bitline for MRAM devices | Michael C. Gaidis, Carl Radens, Lawrence A. Clevenger, Timothy J. Dalton, Louis L. Hsu +1 more | 2009-12-22 |
| 7622386 | Method for improved formation of nickel silicide contacts in semiconductor devices | Anita Madan, Robert J. Purtell, Jun-Keun Kwak | 2009-11-24 |
| 7598545 | Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices | Eduard A. Cartier, Matthew W. Copel, Bruce B. Doris, Rajarao Jammy, Young-Hee Kim +3 more | 2009-10-06 |
| 7585765 | Formation of oxidation-resistant seed layer for interconnect applications | Chih-Chao Yang, Nancy R. Klymko, Christopher C. Parks | 2009-09-08 |
| 7576003 | Dual liner capping layer interconnect structure and method | Chih-Chao Yang, Haining Yang | 2009-08-18 |
| 7566651 | Low contact resistance metal contact | Chih-Chao Yang, Haining Yang | 2009-07-28 |