Issued Patents All Time
Showing 51–75 of 399 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11138514 | Review machine learning system | Luhui Hu, Ziang Hu | 2021-10-05 |
| 11127623 | Single diffusion cut for gate structures | Ruilong Xie, Jessica Dechene | 2021-09-21 |
| 11121023 | FinFET device comprising a single diffusion break with an upper surface that is substantially coplanar with an upper surface of a fin | Jiehui Shu, Hong Yu, Jinping Liu | 2021-09-14 |
| 11114542 | Semiconductor device with reduced gate height budget | Haigou Huang | 2021-09-07 |
| 11100406 | Knowledge network platform | Luhui Hu, Ziang Hu | 2021-08-24 |
| 11094827 | Semiconductor devices with uniform gate height and method of forming same | Yanping Shen, Xiaoxiao Zhang, Shesh Mani Pandey | 2021-08-17 |
| 11031389 | Semiconductor structures over active region and methods of forming the structures | Jiehui Shu | 2021-06-08 |
| 11011604 | Semiconductor device with recessed source/drain contacts and a gate contact positioned above the active region | Min-hwa Chi | 2021-05-18 |
| 11004953 | Mask-free methods of forming structures in a semiconductor device | Rinus Tek Po Lee, Jiehui Shu, Hong Yu, Wei Hong | 2021-05-11 |
| 10998422 | Methods, apparatus and system for a self-aligned gate cut on a semiconductor device | Laertis Economikos, Ruilong Xie | 2021-05-04 |
| 10978566 | Middle of line structures | Guowei Xu, Keith H. Tabakman, Viraj Sardesai | 2021-04-13 |
| 10971583 | Gate cut isolation including air gap, integrated circuit including same and related method | Hong Yu, Jiehui Shu | 2021-04-06 |
| 10957578 | Single diffusion break device for FDSOI | Wei Hong, Hsien-Ching Lo, Zhenyu Hu, Liu Jiang | 2021-03-23 |
| 10950692 | Methods of forming air gaps between source/drain contacts and the resulting devices | Ruilong Xie, Vimal Kamineni, Shesh Mani Pandey | 2021-03-16 |
| 10950610 | Asymmetric gate cut isolation for SRAM | Bipul C. Paul, Ruilong Xie, Julien Frougier, Daniel Chanemougame | 2021-03-16 |
| 10937786 | Gate cut structures | Ruilong Xie, Laertis Economikos | 2021-03-02 |
| 10937693 | Methods, apparatus and system for a local interconnect feature over an active region in a finFET device | Ruilong Xie, Andreas Knorr, Haiting Wang | 2021-03-02 |
| 10923469 | Vertical resistor adjacent inactive gate over trench isolation | Guowei Xu, Jiehui Shu, Ruilong Xie, Yurong Wen, Garo Derderian +2 more | 2021-02-16 |
| 10911382 | Personalized message priority classification | Jiangsheng Yu | 2021-02-02 |
| 10896853 | Mask-free methods of forming structures in a semiconductor device | Jiehui Shu, Rinus Tek Po Lee, Wei Hong, Hong Yu | 2021-01-19 |
| 10892338 | Scaled gate contact and source/drain cap | Ruilong Xie, Jae Gon Lee | 2021-01-12 |
| 10886178 | Device with highly active acceptor doping and method of production thereof | Tek Po Rinus Lee, Annie Levesque, Qun Gao, Rishikesh Krishnan, Bharat Krishnan +1 more | 2021-01-05 |
| 10879073 | Insulating gate separation structure for transistor devices | Chanro Park, Ruilong Xie, Laertis Economikos, Andre P. Labonte | 2020-12-29 |
| 10879171 | Vertically oriented metal silicide containing e-fuse device | Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh | 2020-12-29 |
| 10879180 | FinFET with etch-selective spacer and self-aligned contact capping layer | Guowei Xu, Scott Beasor, Ruilong Xie | 2020-12-29 |