Issued Patents All Time
Showing 76–100 of 399 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10872979 | Spacer structures for a transistor device | Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie +2 more | 2020-12-22 |
| 10833171 | Spacer structures on transistor devices | Yanping Shen, Jiehui Shu | 2020-11-10 |
| 10832967 | Tapered fin-type field-effect transistors | Ruilong Xie, Garo Derderian | 2020-11-10 |
| 10825913 | Methods, apparatus, and manufacturing system for FinFET devices with reduced parasitic capacitance | Haiting Wang, Ruilong Xie | 2020-11-03 |
| 10825741 | Methods of forming single diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products | Ruilong Xie | 2020-11-03 |
| 10825897 | Formation of enhanced faceted raised source/drain EPI material for transistor devices | Wei Hong, George R. Mulfinger, Liu Jiang, Zhenyu Hu | 2020-11-03 |
| 10825910 | Shaped gate caps in dielectric-lined openings | Shesh Mani Pandey | 2020-11-03 |
| 10818659 | FinFET having upper spacers adjacent gate and source/drain contacts | Haiting Wang, Guowei Xu, Scott Beasor | 2020-10-27 |
| 10818498 | Shaped gate caps in spacer-lined openings | Yanping Shen, Haiting Wang | 2020-10-27 |
| 10811422 | Semiconductor recess to epitaxial regions and related integrated circuit structure | Yanping Shen, Wei Hong, David Paul Brunco | 2020-10-20 |
| 10811409 | Method of manufacturing FinFET with reduced parasitic capacitance and FinFET structure formed thereby | Jiehui Shu, Guowei Xu, Jian Gao | 2020-10-20 |
| 10811319 | Middle of line structures | Ruilong Xie | 2020-10-20 |
| 10804379 | FinFET device and method of manufacturing | Ruilong Xie, Scott Beasor | 2020-10-13 |
| 10797046 | Resistor structure for integrated circuit, and related methods | Jiehui Shu | 2020-10-06 |
| 10797049 | FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming same | Haiting Wang, Chung Foong Tan, Guowei Xu, Ruilong Xie, Scott Beasor +1 more | 2020-10-06 |
| 10790363 | IC structure with metal cap on cobalt layer and methods of forming same | Laertis Economikos, Kevin J. Ryan, Ruilong Xie | 2020-09-29 |
| 10784143 | Trench isolation preservation during transistor fabrication | Haiting Wang, Guowei Xu, Yue Zhong | 2020-09-22 |
| 10784195 | Electrical fuse formation during a multiple patterning process | Jiehui Shu, Xiaoqiang Zhang, Haizhou Yin, Moosung Chae, Jinping Liu | 2020-09-22 |
| 10777637 | Integrated circuit product with a multi-layer single diffusion break and methods of making such products | Hong Yu, Jiehui Shu | 2020-09-15 |
| 10777642 | Formation of enhanced faceted raised source/drain epi material for transistor devices | Wei Hong, George R. Mulfinger, Liu Jiang, Zhenyu Hu | 2020-09-15 |
| 10763176 | Transistor with a gate structure comprising a tapered upper surface | Scott Beasor, Haiting Wang | 2020-09-01 |
| 10756184 | Faceted epitaxial source/drain regions | George R. Mulfinger, Timothy J. McArdle, Judson R. Holt, Steffen Sichler, Omur Isil Aydin +3 more | 2020-08-25 |
| 10741451 | FinFET having insulating layers between gate and source/drain contacts | Laertis Economikos, Shesh Mani Pandey, Chanro Park, Ruilong Xie | 2020-08-11 |
| 10741656 | Wraparound contact surrounding source/drain regions of integrated circuit structures and method of forming same | Ruilong Xie, Shesh Mani Pandey, Laertis Economikos | 2020-08-11 |
| 10734233 | FinFET with high-k spacer and self-aligned contact capping layer | Guowei Xu, Keith H. Tabakman | 2020-08-04 |