Issued Patents All Time
Showing 51–75 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11018221 | Air gap regions of a semiconductor device | Chun Yu Wong, Yong Shi, Xiaoming Yang, Liu Jiang | 2021-05-25 |
| 11004748 | Semiconductor devices with wide gate-to-gate spacing | Sipeng Gu, Jiehui Shu | 2021-05-11 |
| 10971625 | Epitaxial structures of a semiconductor device having a wide gate pitch | Michael V. Aquilino, Daniel Jaeger, Man Gu, Bradley Morgenfeld, KAVYA SREE DUGGIMPUDI +1 more | 2021-04-06 |
| 10937693 | Methods, apparatus and system for a local interconnect feature over an active region in a finFET device | Ruilong Xie, Andreas Knorr, Hui Zang | 2021-03-02 |
| 10937685 | Diffusion break structures in semiconductor devices | Sipeng Gu, Jiehui Shu | 2021-03-02 |
| 10872979 | Spacer structures for a transistor device | Hui Zang, Chung Foong Tan, Guowei Xu, Yue Zhong, Ruilong Xie +2 more | 2020-12-22 |
| 10840245 | Semiconductor device with reduced parasitic capacitance | Shesh Mani Pandey, Jiehui Shu | 2020-11-17 |
| 10833169 | Metal gate for a field effect transistor and method | Tao Chu, Rongtao Lu, Ayse M. Ozbek, Wei Ma | 2020-11-10 |
| 10832839 | Metal resistors with a non-planar configuration | Scott Beasor, Sipeng Gu, Jiehui Shu | 2020-11-10 |
| 10832965 | Fin reveal forming STI regions having convex shape between fins | Yiheng Xu, Qun Gao, Scott Beasor, Kyung-Bum Koo, Ankur Arya | 2020-11-10 |
| 10832966 | Methods and structures for a gate cut | Chang Seo Park, Shimpei Yamaguchi, Junsic Hong, Yong Yang, Scott Beasor | 2020-11-10 |
| 10833067 | Metal resistor structure in at least one cavity in dielectric over TS contact and gate structure | Sipeng Gu, Jiehui Shu, Scott Beasor, Zhenyu Hu | 2020-11-10 |
| 10825913 | Methods, apparatus, and manufacturing system for FinFET devices with reduced parasitic capacitance | Hui Zang, Ruilong Xie | 2020-11-03 |
| 10818659 | FinFET having upper spacers adjacent gate and source/drain contacts | Hui Zang, Guowei Xu, Scott Beasor | 2020-10-27 |
| 10818498 | Shaped gate caps in spacer-lined openings | Yanping Shen, Hui Zang | 2020-10-27 |
| 10818557 | Integrated circuit structure to reduce soft-fail incidence and method of forming same | Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil Kumar Singh, Ravi Prakash Srivastava +1 more | 2020-10-27 |
| 10797049 | FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming same | Hui Zang, Chung Foong Tan, Guowei Xu, Ruilong Xie, Scott Beasor +1 more | 2020-10-06 |
| 10784143 | Trench isolation preservation during transistor fabrication | Guowei Xu, Hui Zang, Yue Zhong | 2020-09-22 |
| 10763176 | Transistor with a gate structure comprising a tapered upper surface | Hui Zang, Scott Beasor | 2020-09-01 |
| 10727133 | Method of forming gate structure with undercut region and resulting device | Qun Gao, Balaji Kannan, Shesh Mani Pandey | 2020-07-28 |
| 10714376 | Method of forming semiconductor material in trenches having different widths, and related structures | Chih-Chiang Chang, Haifeng Sheng, Jiehui Shu, Haigou Huang, Pei Liu +2 more | 2020-07-14 |
| 10707175 | Asymmetric overlay mark for overlay measurement | Wei Zhao, Minghao Tang, Rui Chen, Dongyue Yang, Erik Geiss +1 more | 2020-07-07 |
| 10707303 | Method, apparatus, and system for improving scaling of isolation structures for gate, source, and/or drain contacts | Hui Zang, Zhenyu Hu | 2020-07-07 |
| 10700173 | FinFET device with a wrap-around silicide source/drain contact structure | Yi Qi, Hsien-Ching Lo, Hong Yu, Yanping Shen, Wei Hong +4 more | 2020-06-30 |
| 10692987 | IC structure with air gap adjacent to gate structure and methods of forming same | Guowei Xu, Hui Zang | 2020-06-23 |