Issued Patents All Time
Showing 101–125 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10249616 | Methods of forming a resistor structure between adjacent transistor gates on an integrated circuit product and the resulting devices | Hui Zang, Manfred Eller, Daniel Jaeger | 2019-04-02 |
| 10192746 | STI inner spacer to mitigate SDB loading | Ashish Jha, Hui Zhan, Hong Yu, Zhenyu Hu, Edward Reis +1 more | 2019-01-29 |
| 10164010 | Finfet diffusion break having protective liner in fin insulator | Wei Hong, Hsien-Ching Lo, Yanping Shen, Yi Qi, Yongjun Shi +2 more | 2018-12-25 |
| 10153209 | Insulating gate separation structure and methods of making same | Guowei Xu, Hui Zang, Yue Zhong | 2018-12-11 |
| 10121788 | Fin-type field effect transistors with single-diffusion breaks and method | Wei Zhao, Hong Yu, Xusheng Wu, Hui Zang, Zhenyu Hu | 2018-11-06 |
| 10083874 | Gate cut method | Hong Yu, Zhenyu Hu | 2018-09-25 |
| 10008385 | Enlarged sacrificial gate caps for forming self-aligned contacts | Ashish Jha, Chih-Chiang Chang, Mitchell Rutkowski | 2018-06-26 |
| 9984933 | Silicon liner for STI CMP stop in FinFET | Yiheng Xu, Wei Zhao, Todd B. Abrams, Jiehui Shu, Jinping Liu +1 more | 2018-05-29 |
| 9935104 | Fin-type field effect transistors with single-diffusion breaks and method | Wei Zhao, Hong Yu, Xusheng Wu, Hui Zang, Zhenyu Hu | 2018-04-03 |
| 9698269 | Conformal nitridation of one or more fin-type transistor layers | Wei Tong, Tien Ying Luo, Yan Ping SHEN, Feng Zhou, Jun Lian +4 more | 2017-07-04 |
| 9653583 | Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices | Wei Zhao, Hongliang Shen, Zhenyu Hu, Min-hwa Chi | 2017-05-16 |
| 9443771 | Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology | Yanping Shen, Min-hwa Chi, Ashish Jha | 2016-09-13 |
| 9425100 | Methods of facilitating fabricating transistors | Zhaoxu Shen, Min-hwa Chi, Qin Wang, Meixiong Zhao, Duohui Bei | 2016-08-23 |
| 9418899 | Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology | Yan Ping SHEN, Min-hwa Chi, Xusheng Wu, Weihua Tong | 2016-08-16 |
| 9379186 | Fet structure for minimum size length/width devices for performance boost and mismatch reduction | Qin Wang, Min-hwa Chi, Meixiong Zhao, Zhaoxu Shen, Lucas M. Salazar +1 more | 2016-06-28 |
| 9331159 | Fabricating transistor(s) with raised active regions having angled upper surfaces | Ashish Jha, Yan Ping SHEN, Wei Tong, Min-hwa Chi | 2016-05-03 |
| 9312145 | Conformal nitridation of one or more fin-type transistor layers | Wei Tong, Tien Ying Luo, Yan Ping SHEN, Feng Zhou, Jun Lian +4 more | 2016-04-12 |
| 9293580 | Lightly doped source/drain last method for dual-epi integration | Ka-Hing Fung, Han-Ting Tsai | 2016-03-22 |
| 9209258 | Depositing an etch stop layer before a dummy cap layer to improve gate performance | Feng Zhou, Tien Ying Luo, Padmaja NAGAIAH, Jean-Baptiste Laloe, Isabelle Ferain +1 more | 2015-12-08 |
| 9202697 | Forming a gate by depositing a thin barrier layer on a titanium nitride cap | Tien Ying Luo, Feng Zhou, Yan Ping SHEN, Haoran SHI, Wei Tong +2 more | 2015-12-01 |
| 9147572 | Using sacrificial oxide layer for gate length tuning and resulting device | Ashish Jha, Meng Luo, Yong Meng Lee | 2015-09-29 |
| 9093557 | Completing middle of line integration allowing for self-aligned contacts | Guillaume Bouche | 2015-07-28 |
| 8952459 | Gate structure having lightly doped region | Fung Ka Hing, Han-Ting Tsai, Chun-Fai Cheng, Wei-Yuan Lu, Hsien-Ching Lo +1 more | 2015-02-10 |
| 8900940 | Reducing gate height variance during semiconductor device formation | Ashish Jha, Tae Hoon Kim, Tae Hoon Lee, Chang Ho Maeng, Songkram Srivathanakul | 2014-12-02 |
| 8722485 | Integrated circuits having replacement gate structures and methods for fabricating the same | Wei Tong, Yiqun Liu, Tae Hoon Kim, Seung Kim, Huang Liu | 2014-05-13 |