DH

David V. Horak

Globalfoundries: 20 patents #152 of 4,424Top 4%
GP Globalfoundries Singapore Pte.: 5 patents #141 of 828Top 20%
FS Freeescale Semiconductor: 2 patents #1,335 of 3,767Top 40%
Samsung: 1 patents #49,284 of 75,807Top 70%
GU Globalfoundries U.S.: 1 patents #22 of 211Top 15%
📍 South Burlington, VT: #1 of 1,136 inventorsTop 1%
🗺 Vermont: #5 of 4,968 inventorsTop 1%
Overall (All Time): #800 of 4,157,543Top 1%
365
Patents All Time

Issued Patents All Time

Showing 276–300 of 365 patents

Patent #TitleCo-InventorsDate
6798017 Vertical dual gate field effect transistor Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, James M. Leas, William H. Ma +1 more 2004-09-28
6767789 Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby Gary B. Bronner, Toshiharu Furukawa, Jack A. Mandelman 2004-07-27
6759315 Method for selective trimming of gate structures and apparatus formed thereby Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Paul A. Rabidoux 2004-07-06
6749969 Reverse tone process for masks Robert K. Leidy 2004-06-15
6713835 Method for manufacturing a multi-level interconnect structure Charles W. Koburger, III, Peter H. Mitchell, Larry Nesbit 2004-03-30
6680514 Contact capping local interconnect Robert M. Geffken, Anthony K. Stamper 2004-01-20
6656807 Grooved planar DRAM transfer device using buried pocket Gary B. Bronner, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Jack A. Mandelman 2003-12-02
6653737 Interconnection structure and method for fabricating same William A. Klaasen, Thomas L. McDevitt, Mark P. Murray, Anthony K. Stamper 2003-11-25
6627477 Method of assembling a plurality of semiconductor devices having different thickness Mark C. Hakey, Steven J. Holmes, Harold G. Linde, Edmund J. Sprogis 2003-09-30
6614074 Grooved planar DRAM transfer device using buried pocket Gary B. Bronner, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Jack A. Mandelman 2003-09-02
6605534 Selective deposition of a conductive material Dean S. Chung, Erick G. Walton 2003-08-12
6596597 Method of manufacturing dual gate logic devices Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, William H. Ma 2003-07-22
6583462 Vertical DRAM having metallic node conductor Toshiharu Furukawa, Rajarao Jammy, Thomas S. Kanarsky, Jeffrey J. Welser, Steven J. Holmes +1 more 2003-06-24
6531724 Borderless gate structures Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Paul A. Rabidoux 2003-03-11
6506660 Semiconductor with nanoscale features Steven J. Holmes, Charles T. Black, David J. Frank, Toshiharu Furukawa, Mark C. Hakey +3 more 2003-01-14
6506653 Method using disposable and permanent films for diffusion and implant doping Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, William H. Ma, Patricia Marmillion +1 more 2003-01-14
6503827 Method of reducing planarization defects Susan G. Bombardier, Paul M. Feeney, Robert M. Geffken, Matthew J. Rutten 2003-01-07
6489207 Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes 2002-12-03
6452265 Multi-chip module utilizing a nonconductive material surrounding the chips that has a similar coefficient of thermal expansion Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Rosemary A. Previti-Kelly, Edmund J. Sprogis 2002-09-17
6444402 Method of making differently sized vias and lines on the same lithography level Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, William H. Ma 2002-09-03
6440801 Structure for folded architecture pillar memory cell Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Howard L. Kalter, Jack A. Mandelman +2 more 2002-08-27
6441464 Gate oxide stabilization by means of germanium components in gate conductor Steven J. Holmes, Mark C. Hakey, Toshiharu Furukawa 2002-08-27
6436814 Interconnection structure and method for fabricating same William A. Klaasen, Thomas L. McDevitt, Mark P. Murray, Anthony K. Stamper 2002-08-20
6429045 Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, H. Bernhard Pogge, Edmund J. Sprogis +1 more 2002-08-06
6429080 Multi-level dram trench store utilizing two capacitors and two plates Toshiharu Furukawa, Howard L. Kalter 2002-08-06