Issued Patents All Time
Showing 126–150 of 190 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6444381 | Electron beam flood exposure technique to reduce the carbon contamination | Bhanwar Singh, Ramkumar Subramanian, Michael K. Templeton, Khoi A. Phan, Bryan K. Choo +1 more | 2002-09-03 |
| 6444373 | Modification of mask layout data to improve mask fidelity | Ramkumar Subramanian, Khoi A. Phan, Bhanwar Singh | 2002-09-03 |
| 6439963 | System and method for mitigating wafer surface disformation during chemical mechanical polishing (CMP) | Bhanwar Singh, Ursula Q. Quinto | 2002-08-27 |
| 6441418 | Spacer narrowed, dual width contact for charge gain reduction | Jeffrey A. Shields | 2002-08-27 |
| 6441349 | System for facilitating uniform heating temperature of photoresist | Bhanwar Singh, Sanjay K. Yedur | 2002-08-27 |
| 6440289 | Method for improving seed layer electroplating for semiconductor | Christy Mei-Chu Woo, Bhanwar Singh | 2002-08-27 |
| 6436766 | Process for fabricating high density memory cells using a polysilicon hard mask | David K. Foote, Fei Wang, Dawn Hopper, Stephen Keetai Park, Jack F. Thomas +2 more | 2002-08-20 |
| 6426301 | Reduction of via etch charging damage through the use of a conducting hard mask | Jeffrey A. Shields, Ramkumar Subramanian, Allen S. Yu | 2002-07-30 |
| 6423479 | Cleaning carbon contamination on mask using gaseous phase | Ramkumar Subramanian, Khoi A. Phan, Bhanwar Singh, Sanjay K. Yedur, Bryan K. Choo | 2002-07-23 |
| 6422918 | Chemical-mechanical polishing of photoresist layer | Steven C. Avanzino, Bhanwar Singh, Alvin M. Dangca | 2002-07-23 |
| 6420104 | Method of reducing contact size by spacer filling | Stephen Keetai Park, Guarionex Morales | 2002-07-16 |
| 6416933 | Method to produce small space pattern using plasma polymerization layer | Bhanwar Singh, Wenge Yang | 2002-07-09 |
| 6413857 | Method of creating ground to avoid charging in SOI products | Ramkumar Subramanian, Bhanwar Singh | 2002-07-02 |
| 6406960 | Process for fabricating an ONO structure having a silicon-rich silicon nitride layer | Dawn Hopper, David K. Foote, Arvind Halliyal | 2002-06-18 |
| 6399446 | Process for fabricating high density memory cells using a metallic hard mask | David K. Foote, Fei Wang, Dawn Hopper, Stephen Keetai Park, Jack F. Thomas +2 more | 2002-06-04 |
| 6376013 | Multiple nozzles for dispensing resist | Bhanwar Singh, Sanjay K. Yedur, Michael K. Templeton | 2002-04-23 |
| 6376308 | Process for fabricating an EEPROM device having a pocket substrate region | Fei Wang, David K. Foote, George J. Kluth | 2002-04-23 |
| 6372614 | Dual damascene method for backened metallization using poly stop layers | Ramkumar Subramanian, Bhanwar Singh | 2002-04-16 |
| 6371134 | Ozone cleaning of wafers | Ramkumar Subramanian, Khoi A. Phan, Bhanwar Singh, Sanjay K. Yedur, Bryan K. Choo | 2002-04-16 |
| 6362052 | Use of an etch to reduce the thickness and around the edges of a resist mask during the creation of a memory cell | Fei Wang, George J. Kluth, Ursula Q. Quinto | 2002-03-26 |
| 6352817 | Methodology for mitigating formation of t-tops in photoresist | Bhanwar Singh, Steven C. Avanzino | 2002-03-05 |
| 6339955 | Thickness measurement using AFM for next generation lithography | Khoi A. Phan, Bhanwar Singh | 2002-01-22 |
| 6335152 | Use of RTA furnace for photoresist baking | Ramkumar Subramanian, Michael K. Templeton, Bhanwar Singh | 2002-01-01 |
| 6329124 | Method to produce high density memory cells and small spaces by using nitride spacer | Bhanwar Singh, Michael K. Templeton | 2001-12-11 |
| 6326231 | Use of silicon oxynitride ARC for metal layers | Ramkumar Subramanian, Bhanwar Singh, Sanjay K. Yedur, Marina V. Plat, Christopher F. Lyons +1 more | 2001-12-04 |