Issued Patents All Time
Showing 151–175 of 190 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6326268 | Method of fabricating a MONOS flash cell using shallow trench isolation | Steven K. Park, Fei Wang | 2001-12-04 |
| 6322009 | Common nozzle for resist development | Ramkumar Subramanian, Khoi A. Phan, Bhanwar Singh | 2001-11-27 |
| 6297143 | Process for forming a bit-line in a MONOS device | David K. Foote, Fei Wang, Steven K. Park | 2001-10-02 |
| 6291135 | Ionization technique to reduce defects on next generation lithography mask during exposure | Khoi A. Phan, Bhanwar Singh | 2001-09-18 |
| 6287917 | Process for fabricating an MNOS flash memory device | Stephen Keetai Park, Tim Thurgate | 2001-09-11 |
| 6277544 | Reverse lithographic process for semiconductor spaces | Bhanwar Singh, Ursula Q. Quinto | 2001-08-21 |
| 6274289 | Chemical resist thickness reduction process | Ramkumar Subramanian, Michael K. Templeton, Ursula Q. Quinto | 2001-08-14 |
| 6270579 | Nozzle arm movement for resist development | Ramkumar Subramanian, Khoi A. Phan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur | 2001-08-07 |
| 6269322 | System and method for wafer alignment which mitigates effects of reticle rotation and magnification on overlay | Michael K. Templeton, Kathleen R. Early, Terry Manchester | 2001-07-31 |
| 6265273 | Method of forming rectangular shaped spacers | Steven C. Avanzino, Stephen Keetai Park, Jeffrey A. Shields, Larry Wang, Guarionex Morales | 2001-07-24 |
| 6265294 | Integrated circuit having double bottom anti-reflective coating layer | Stephen Keetai Park, Guarionex Morales, Jeff Shields | 2001-07-24 |
| 6261960 | High density contacts having rectangular cross-section for dual damascene applications | Allen S. Yu, Paul J. Steffan | 2001-07-17 |
| 6262484 | Dual damascene method for backened metallization using poly stop layers | Ramkumar Subramanian, Bhanwar Singh | 2001-07-17 |
| 6261904 | Dual bit isolation scheme for flash devices | Tuan Pham, Mike Templeton | 2001-07-17 |
| 6251570 | Resist developer saving system using material to reduce surface tension and wet resist surface | Khoi A. Phan, Ramkumar Subramanian, Bhanwar Singh | 2001-06-26 |
| 6248635 | Process for fabricating a bit-line in a monos device using a dual layer hard mask | David K. Foote, Hideki Komori, Steven K. Park | 2001-06-19 |
| 6248175 | Nozzle arm movement for resist development | Ramkumar Subramanian, Khoi A. Phan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur | 2001-06-19 |
| 6245493 | Method for reducing surface reflectivity by increasing surface roughness | Bhanwar Singh, Sanjay K. Yedur, Michael K. Templeton, Christopher F. Lyons | 2001-06-12 |
| 6242305 | Process for fabricating a bit-line using buried diffusion isolation | David K. Foote, Hideki Komori, Fei Wang | 2001-06-05 |
| 6238830 | Active control of temperature in scanning probe lithography and maskless lithograpy | Michael K. Templeton, Bhanwar Singh | 2001-05-29 |
| 6221777 | Reverse lithographic process for semiconductor vias | Bhanwar Singh, Ursula Q. Quinto | 2001-04-24 |
| 6210846 | Exposure during rework for enhanced resist removal | Ursula Q. Quinto, Bhanwar Singh | 2001-04-03 |
| 6207502 | Method of using source/drain nitride for periphery field oxide and bit-line oxide | Kenneth Wo-Wai Au, David K. Foote, Steven K. Park, Fei Wang | 2001-03-27 |
| 6207582 | Native oxide removal with fluorinated chemistry before cobalt silicide formation using nitride spacers | Jeffrey A. Shields | 2001-03-27 |
| 6197455 | Lithographic mask repair using a scanning tunneling microscope | Sanjay K. Yedur, Bhanwar Singh, Michael K. Templeton, Kathleen R. Early | 2001-03-06 |