Issued Patents 2021
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11205630 | Vias in composite IC chip structures | Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Mauro Kobrinksy, Van H. Le +1 more | 2021-12-21 |
| 11201221 | Backside contact structures and fabrication for metal on both sides of devices | Rishabh Mehandru, Aaron D. Lilak, Kimin Jun | 2021-12-14 |
| 11139241 | Integrated circuit device with crenellated metal trace layout | Mauro J. Kobrinsky, Mark Bohr, Tahir Ghani, Rishabh Mehandru, Ranjith Kumar | 2021-10-05 |
| 11107924 | Systems and methods to reduce FinFET gate capacitance | Aaron D. Lilak, Rishabh Mehandru | 2021-08-31 |
| 11107811 | Metallization structures under a semiconductor device layer | Aaron D. Lilak, Rishabh Mehandru, Stephen M. Cea | 2021-08-31 |
| 11094672 | Composite IC chips including a chiplet embedded within metallization layers of a host IC chip | Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Gerald Pasdast, Van H. Le | 2021-08-17 |
| 11075119 | Vertically stacked transistors in a pin | Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Rishabh Mehandru | 2021-07-27 |
| 11075202 | Bottom fin trim isolation aligned with top gate for stacked device architectures | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru | 2021-07-27 |
| 11049861 | Method, device and system to provide capacitance for a dynamic random access memory cell | Aaron D. Lilak, Rishabh Mehandru, Donald W. Nelson, Stephen M. Cea | 2021-06-29 |
| 11037817 | Apparatus with multi-wafer based device and method for forming such | Anup Pancholi, Prashant Majhi, Paul B. Fischer | 2021-06-15 |
| 11037916 | Apparatus with multi-wafer based device comprising embedded active devices and method for forming such | Anup Pancholi, Prashant Majhi, Paul B. Fischer | 2021-06-15 |
| 11011537 | Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability | Aaron D. Lilak, Patrick Theofanis, Rishabh Mehandru, Stephen M. Cea | 2021-05-18 |
| 10998302 | Packaged device with a chiplet comprising memory resources | Adel A. Elsherbini, Van H. Le, Johanna M. Swan, Shawna M. Liff, Gerald Pasdast +1 more | 2021-05-04 |
| 10978590 | Methods and apparatus to remove epitaxial defects in semiconductors | Aaron D. Lilak, Rishabh Mehandru, Patrick H. Keys | 2021-04-13 |
| 10944399 | Multi-level spin logic | Sasikanth Manipatruni, Ian A. Young, Dmitri E. Nikonov, Uygar E. Avci, Anurag Chaudhry | 2021-03-09 |
| 10937665 | Methods and apparatus for gettering impurities in semiconductors | Aaron D. Lilak, Harold W. Kennel, Rishabh Mehandru, Stephen M. Cea | 2021-03-02 |
| 10910405 | Backside fin recess control with multi-HSI option | Aaron D. Lilak, Stephen M. Cea, Rishabh Mehandru, Cory E. Weber | 2021-02-02 |
| 10896847 | Techniques for revealing a backside of an integrated circuit device, and associated configurations | Il-Seok Son, Colin T. Carver, Paul B. Fischer, Kimin Jun | 2021-01-19 |
| 10892215 | Metal on both sides with power distributed through the silicon | Donald W. Nelson, Mark Bohr | 2021-01-12 |
| 10892337 | Backside source/drain replacement for semiconductor devices with metallization on both sides | Glenn A. Glass, Karthik Jambunathan, Anand S. Murthy, Chandra S. Mohapatra, Mauro J. Kobrinsky | 2021-01-12 |
| 10886217 | Integrated circuit device with back-side interconnection to deep source/drain semiconductor | Mauro J. Kobrinsky, Mark Bohr, Tahir Ghani, Rishabh Mehandru | 2021-01-05 |