Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Packaged device with a chiplet comprising memory resources

Packaged device with a chiplet comprising memory resources

US Patent 10998302 · Granted May 4, 2021

Estimated economic value: $37,420,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

On-package die-to-die (D2D) interconnect for memory using universal chiplet inte2025
Vertically spaced intra-level interconnect line metallization for integrated cir2025
Retimers to extend a die-to-die interconnect2025
Die-to-die interconnect protocol layer2025
Microelectronic assemblies with communication networks2025
Microelectronic assemblies with communication networks2025
Microelectronic assemblies with communication networks2025
Packaging architecture with intermediate routing layers2025
Packaging architecture with intermediate routing layers2025
Packaging architecture with intermediate routing layers2025
Clock interpolation system for eye-centering2025
Apparatus and method of manufacturing a vertically disaggregated photonic device2025