Issued Patents 2021
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11195919 | Method of fabricating a semiconductor device with strained SiGe fins and a Si cladding layer | Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn +1 more | 2021-12-07 |
| 11152461 | Semiconductor layer between source/drain regions and gate spacers | Rishabh Mehandru, Anupama Bowonder, Biswajeet Guha, Tahir Ghani, William Hsu +2 more | 2021-10-19 |
| 11107811 | Metallization structures under a semiconductor device layer | Aaron D. Lilak, Rishabh Mehandru, Patrick Morrow | 2021-08-31 |
| 11094831 | Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device | Rishabh Mehandru, Szuya S. Liao | 2021-08-17 |
| 11049861 | Method, device and system to provide capacitance for a dynamic random access memory cell | Aaron D. Lilak, Patrick Morrow, Rishabh Mehandru, Donald W. Nelson | 2021-06-29 |
| 11037923 | Through gate fin isolation | Mark Bohr, Barbara A. Chappell | 2021-06-15 |
| 11011537 | Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability | Aaron D. Lilak, Patrick Theofanis, Patrick Morrow, Rishabh Mehandru | 2021-05-18 |
| 10991799 | Silicon and silicon germanium nanowire structures | Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Martin D. Giles, Annalisa Cappellani +3 more | 2021-04-27 |
| 10991696 | Vertically stacked devices with self-aligned regions formed by direct self assembly (DSA) processing | Aaron D. Lilak, Patrick Theofanis, Cory E. Weber, Rishabh Mehandru | 2021-04-27 |
| 10937665 | Methods and apparatus for gettering impurities in semiconductors | Aaron D. Lilak, Harold W. Kennel, Patrick Morrow, Rishabh Mehandru | 2021-03-02 |
| 10910405 | Backside fin recess control with multi-HSI option | Aaron D. Lilak, Patrick Morrow, Rishabh Mehandru, Cory E. Weber | 2021-02-02 |
| 10892326 | Removal of a bottom-most nanowire from a nanowire device stack | Aaron D. Lilak, Patrick H. Keys, Sean T. Ma, Rishabh Mehandru | 2021-01-12 |
| 10886272 | Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices | Rishabh Mehandru, Anupama Bowonder, Anand S. Murthy, Tahir Ghani | 2021-01-05 |