Issued Patents 2021
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11201129 | Designs and methods for conductive bumps | Valery M. Dubin, Sridhar Balakrishnan | 2021-12-14 |
| 11139241 | Integrated circuit device with crenellated metal trace layout | Patrick Morrow, Mauro J. Kobrinsky, Tahir Ghani, Rishabh Mehandru, Ranjith Kumar | 2021-10-05 |
| 11127712 | Functionally redundant semiconductor dies and package | Wilfred Gomes, Udi Sherel, Leonard NEIBERG, Nevine Nassif, Wesley McCullough | 2021-09-21 |
| 11068640 | Power shared cell architecture | Ranjith Kumar, Ruth A. Brain, Marni Nabors, Tai-Hsuan Wu, Sourav Chakravarty | 2021-07-20 |
| 11043459 | Multiple reticle field semiconductor devices | Edward A. Burton, Murray Fitzpatrick Kelley, Shawn Michael Klauser | 2021-06-22 |
| 11037923 | Through gate fin isolation | Stephen M. Cea, Barbara A. Chappell | 2021-06-15 |
| 11024601 | Hyperchip | Wilfred Gomes, Rajesh Kumar, Pooya Tadayon, Doug B. Ingerly | 2021-06-01 |
| 11004739 | Gate contact structure over active gate and method to fabricate same | Abhijit Jayant Pethe, Tahir Ghani, Clair Webb, Harry Gomez, Annalisa Cappellani | 2021-05-11 |
| 10930557 | Self-aligned contacts | Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2021-02-23 |
| 10892215 | Metal on both sides with power distributed through the silicon | Donald W. Nelson, Patrick Morrow | 2021-01-12 |
| 10886217 | Integrated circuit device with back-side interconnection to deep source/drain semiconductor | Patrick Morrow, Mauro J. Kobrinsky, Tahir Ghani, Rishabh Mehandru | 2021-01-05 |