| 11201221 |
Backside contact structures and fabrication for metal on both sides of devices |
Patrick Morrow, Aaron D. Lilak, Kimin Jun |
2021-12-14 |
$41,312,000 |
| 11152461 |
Semiconductor layer between source/drain regions and gate spacers |
Anupama Bowonder, Biswajeet Guha, Tahir Ghani, Stephen M. Cea, William Hsu +2 more |
2021-10-19 |
$36,352,000 |
| 11152396 |
Semiconductor device having stacked transistors and multiple threshold voltage control |
Aaron D. Lilak, Gilbert Dewey, Willy Rachmady |
2021-10-19 |
$36,352,000 |
| 11139241 |
Integrated circuit device with crenellated metal trace layout |
Patrick Morrow, Mauro J. Kobrinsky, Mark Bohr, Tahir Ghani, Ranjith Kumar |
2021-10-05 |
$23,463,000 |
| 11107811 |
Metallization structures under a semiconductor device layer |
Aaron D. Lilak, Patrick Morrow, Stephen M. Cea |
2021-08-31 |
$22,590,000 |
| 11107924 |
Systems and methods to reduce FinFET gate capacitance |
Aaron D. Lilak, Patrick Morrow |
2021-08-31 |
$22,590,000 |
| 11094831 |
Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device |
Szuya S. Liao, Stephen M. Cea |
2021-08-17 |
$29,127,000 |
| 11094716 |
Source contact and channel interface to reduce body charging from band-to-band tunneling |
Dipanjan Basu, Seung Hoon Sung |
2021-08-17 |
$29,127,000 |
| 11075198 |
Stacked transistor architecture having diverse fin geometry |
Aaron D. Lilak, Cheng-Ying Huang, Gilbert Dewey, Willy Rachmady |
2021-07-27 |
$27,337,000 |
| 11075202 |
Bottom fin trim isolation aligned with top gate for stacked device architectures |
Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Patrick Morrow |
2021-07-27 |
$27,337,000 |
| 11075119 |
Vertically stacked transistors in a pin |
Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Patrick Morrow |
2021-07-27 |
$27,337,000 |
| 11049861 |
Method, device and system to provide capacitance for a dynamic random access memory cell |
Aaron D. Lilak, Patrick Morrow, Donald W. Nelson, Stephen M. Cea |
2021-06-29 |
$34,663,000 |
| 11011620 |
Techniques for increasing channel region tensile strain in n-MOS devices |
Cory E. Weber, Anand S. Murthy, Karthik Jambunathan, Glenn A. Glass, Jiong Zhang +2 more |
2021-05-18 |
$44,170,000 |
| 11011537 |
Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability |
Aaron D. Lilak, Patrick Theofanis, Patrick Morrow, Stephen M. Cea |
2021-05-18 |
$44,170,000 |
| 10991696 |
Vertically stacked devices with self-aligned regions formed by direct self assembly (DSA) processing |
Aaron D. Lilak, Patrick Theofanis, Cory E. Weber, Stephen M. Cea |
2021-04-27 |
$44,593,000 |
| 10978590 |
Methods and apparatus to remove epitaxial defects in semiconductors |
Aaron D. Lilak, Patrick Morrow, Patrick H. Keys |
2021-04-13 |
$58,007,000 |
| 10937665 |
Methods and apparatus for gettering impurities in semiconductors |
Aaron D. Lilak, Harold W. Kennel, Patrick Morrow, Stephen M. Cea |
2021-03-02 |
$34,569,000 |
| 10910405 |
Backside fin recess control with multi-HSI option |
Aaron D. Lilak, Patrick Morrow, Stephen M. Cea, Cory E. Weber |
2021-02-02 |
$28,243,000 |
| 10896907 |
Retrograde transistor doping by heterojunction materials |
Patrick H. Keys, Hei Kam, Aaron A. Budrevich |
2021-01-19 |
$115,732,000 |
| 10896963 |
Semiconductor device contacts with increased contact area |
Tahir Ghani, Szuya S. Liao |
2021-01-19 |
$115,732,000 |
| 10892326 |
Removal of a bottom-most nanowire from a nanowire device stack |
Aaron D. Lilak, Patrick H. Keys, Sean T. Ma, Stephen M. Cea |
2021-01-12 |
$55,416,000 |
| 10886272 |
Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices |
Stephen M. Cea, Anupama Bowonder, Anand S. Murthy, Tahir Ghani |
2021-01-05 |
$27,050,000 |
| 10886217 |
Integrated circuit device with back-side interconnection to deep source/drain semiconductor |
Patrick Morrow, Mauro J. Kobrinsky, Mark Bohr, Tahir Ghani |
2021-01-05 |
$27,050,000 |
