Issued Patents All Time
Showing 76–100 of 102 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9130026 | Crystalline layer for passivation of III-N surface | Han-Chin Chiu, Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai | 2015-09-08 |
| 9093511 | Transistor having high breakdown voltage and method of making the same | Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai | 2015-07-28 |
| 9076854 | Semiconductor device | Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai | 2015-07-07 |
| 9064821 | Silicon dot formation by self-assembly method and selective silicon growth for flash memory | Chih-Ming Chen, Tsung-Yu Chen, Cheng-Te Lee, Szu-Yu Wang, Chung-Yi Yu +1 more | 2015-06-23 |
| 8975641 | Transistor having an ohmic contact by gradient layer and method of making the same | Chen-Hao Chiang, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai | 2015-03-10 |
| 8969882 | Transistor having an ohmic contact by screen layer and method of making the same | Chen-Hao Chiang, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai | 2015-03-03 |
| 8901609 | Transistor having doped substrate and method of making the same | Chi-Ming Chen, Chih-Wen Hsiung, Ming-Chang Ching, Chen-Hao Chiang, Po-Chun Liu +2 more | 2014-12-02 |
| 8816358 | Plasmonic nanostructures for organic image sensors | Shu-Ju Tsai, Yeur-Luen Tu, Cheng-Ta Wu, Cheng-Yuan Tsai, Chia-Shiung Tsai | 2014-08-26 |
| 8802538 | Methods for hybrid wafer bonding | Ping-Yin Liu, Jen-Cheng Liu, Xin-Hua Huang, Hung-Hua Lin, Lan-Lin Chao +1 more | 2014-08-12 |
| 8754446 | Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material | Shwu-Jen Jeng, Byeong Y. Kim, Hasan M. Nayfeh | 2014-06-17 |
| 8513779 | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors | Byeong Y. Kim, Yoichi Otani | 2013-08-20 |
| 8288281 | Method for reducing amine based contaminants | William J. Cote, Anthony K. Stamper, Arthur C. Winslow | 2012-10-16 |
| 8242544 | Semiconductor structure having reduced amine-based contaminants | William J. Cote, Anthony K. Stamper, Arthur C. Winslow | 2012-08-14 |
| 8237247 | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors | Byeong Y. Kim, Yoichi Otani | 2012-08-07 |
| 8053838 | Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets) | Byeong Y. Kim, Mahender Kumar, Huilong Zhu | 2011-11-08 |
| 7993990 | Multiple crystallographic orientation semiconductor structures | Shreesh Narasimha, Paul D. Agnello, Judson R. Holt, Mukesh V. Khare, Byeong Y. Kim +1 more | 2011-08-09 |
| 7803708 | Method for reducing amine based contaminants | William J. Cote, Anthony K. Stamper, Arthur C. Winslow | 2010-09-28 |
| 7790553 | Methods for forming high performance gates and structures thereof | Huilong Zhu, Mahender Kumar, Brian J. Greene, Bachir Dirahoui, Jay William Strane +1 more | 2010-09-07 |
| 7790581 | Semiconductor substrate with multiple crystallographic orientations | Byeong Y. Kim, Woo-Hyeong Lee, Huilong Zhu | 2010-09-07 |
| 7696573 | Multiple crystallographic orientation semiconductor structures | Shreesh Narasimha, Paul D. Agnello, Judson R. Holt, Mukesh V. Khare, Byeong Y. Kim +1 more | 2010-04-13 |
| 7595232 | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors | Byeong Y. Kim, Yoichi Otani | 2009-09-29 |
| 7494918 | Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof | Byeong Y. Kim, Judson R. Holt, Christopher D. Sheraw, Linda Black, Igor Peidous | 2009-02-24 |
| 7491623 | Method of making a semiconductor structure | Shwu-Jen Jeng, Byeong Y. Kim, Hasan M. Nayfeh | 2009-02-17 |
| 7393738 | Subground rule STI fill for hot structure | Byeong Y. Kim, Munir D. Naeem, Frank D. Tamweber | 2008-07-01 |
| 7153776 | Method for reducing amine based contaminants | William J. Cote, Anthony K. Stamper, Arthur C. Winslow | 2006-12-26 |