Issued Patents All Time
Showing 301–325 of 378 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8962464 | Self-alignment for using two or more layers and methods of forming same | Shih-Ming Chang, Ken-Hsien Hsieh, Ming-Feng Shieh, Chih-Ming Lai, Tsai-Sheng Gau | 2015-02-24 |
| 8959460 | Layout decomposition method | Wen-Chun Huang, Ming-Hui Chih, Chia-Ping Chiang, Tsai-Sheng Gau, Jia-Guei Jou +3 more | 2015-02-17 |
| 8954899 | Contour alignment system | Ping-Chieh Wu, Tzu-Chin Lin, Hung-Ting Lu, Wen-Chun Huang | 2015-02-10 |
| 8952329 | 3D image profiling techniques for lithography | I-Chang Shih, Yi-Jie Chen, Chia-Cheng Chang, Feng-Yuan Chiu, Ying-Chou Cheng +2 more | 2015-02-10 |
| 8949749 | Layout design for electron-beam high volume manufacturing | Hung-Chun Wang, Shao-Yun Fang, Tzu-Chin Lin, Wen-Chun Huang | 2015-02-03 |
| 8943445 | Method of merging color sets of layout | Pi-Tsung Chen, Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang +4 more | 2015-01-27 |
| 8910092 | Model based simulation method with fast bias contour for lithography process check | I-Chang Shih, Feng-Yuan Chiu, Ying-Chou Cheng, Chiu Hsiu Chen | 2014-12-09 |
| 8907497 | Semiconductor device with self-aligned interconnects and blocking portions | Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Fang-Yu Fan, Yuan-Te Hou | 2014-12-09 |
| 8898600 | Layout optimization for integrated design | Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Lee-Chung Lu | 2014-11-25 |
| 8850366 | Method for making a mask by forming a phase bar in an integrated circuit design layout | Shuo-Yen Chou, Hoi-Tou Ng, Ken-Hsien Hsieh, Yi-Yin Chen | 2014-09-30 |
| 8850367 | Method of decomposable checking approach for mask alignment in multiple patterning | Chih-Ming Lai, Ken-Hsien Hsieh, Wen-Chun Huang | 2014-09-30 |
| 8841049 | Electron beam data storage system and method for high volume manufacturing | Hung-Chun Wang, Pei-Shiang Chen, Tzu-Chin Lin, Faruk Krecinic, Jeng-Horng Chen +1 more | 2014-09-23 |
| 8835323 | Method for integrated circuit patterning | Ming-Feng Shieh, Tsai-Sheng Gau, Shih-Ming Chang | 2014-09-16 |
| 8828885 | Photo resist trimmed line end space | Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai +1 more | 2014-09-09 |
| 8812999 | Method and system of mask data preparation for curvilinear mask patterns for a device | Wen-Hao Cheng, Chih-Chiang Tu, Shuo-Yen Chou | 2014-08-19 |
| 8806386 | Customized patterning modulation and optimization | Ying-Chou Cheng, Josh J. H. Feng, Tsong-Hua Ou, Luke Lo, Chih-Ming Lai +1 more | 2014-08-12 |
| 8799834 | Self-aligned multiple patterning layout design | Huang-Yu Chen, Li-Chun Tien, Ken-Hsien Hsieh, Jhih-Jian Wang, Chin-Chang Hsu +3 more | 2014-08-05 |
| 8779592 | Via-free interconnect structure with self-aligned metal line interconnections | Yu-Po Tang, Shih-Ming Chang, Ken-Hsien Hsieh | 2014-07-15 |
| 8764995 | Extreme ultraviolet light (EUV) photomasks, and fabrication methods thereof | Ching-Hsu Chang, Hung-Chun Wang, Boren Luo, Wen-Chun Huang | 2014-07-01 |
| 8765329 | Sub-resolution rod in the transition region | Jeng-Shiun Ho, Luke Lo, Ting-Chun Liu, Min Cheng, Jing-Wei Shih +6 more | 2014-07-01 |
| 8762899 | Method for metal correlated via split for double patterning | Burn Jeng Lin, Tsai-Sheng Gau, Wen-Chun Huang | 2014-06-24 |
| 8751976 | Pattern recognition for integrated circuit design | Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Li Cheng, Wen-Chun Huang | 2014-06-10 |
| 8745550 | Fracture aware OPC | Nian-Fuh Cheng, Yu-Po Tang, Chien-Fu Lee, Sheng-Wen Lin, Yong-Cheng Lin +1 more | 2014-06-03 |
| 8745554 | Practical approach to layout migration | Ying-Chou Cheng, Tsong-Hua Ou, Josh J. H. Feng, Cheng-Lung Tsai, Wen-Chun Huang | 2014-06-03 |
| 8739080 | Mask error enhancement factor (MEEF) aware mask rule check (MRC) | Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Chun Huang | 2014-05-27 |