Issued Patents All Time
Showing 151–175 of 187 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8418117 | Chip-level ECO shrink | Huang-Yu Chen, Ho Che Yu, Chung-Hsing Wang, Hsiao-Shu Chao, Yi-Kan Cheng | 2013-04-09 |
| 8418111 | Method and apparatus for achieving multiple patterning technology compliant design layout | Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Ru-Gun Liu, Ken-Hsien Hsieh +3 more | 2013-04-09 |
| 8375347 | Driven metal critical dimension (CD) biasing | Louis Liu, Yao-Ching Ku | 2013-02-12 |
| 8365102 | Method for checking and fixing double-patterning layout | Dio Wang, Ken-Hsien Hsieh, Huang-Yu Chen, Li-Chun Tien, Ru-Gun Liu | 2013-01-29 |
| 8356262 | Cell architecture and method | Li-Chun Tien, Shyue-Shyh Lin, Zhe-Wei Jiang | 2013-01-15 |
| 8350330 | Dummy pattern design for reducing device performance drift | Chien-Chih Kuo, Jian-Yi Li, Sheng-Jier Yang | 2013-01-08 |
| 8347132 | System and method for reducing processor power consumption | Chung-Hsing Wang, Myron Shak, Wei-Pin Changchien, Kuo-Yin Chen, Chi Wei Hu +2 more | 2013-01-01 |
| 8327301 | Routing method for double patterning design | Yi-Kan Cheng, Ru-Gun Liu, Chih-Ming Lai | 2012-12-04 |
| 8286119 | Systematic method for variable layout shrink | Fu-Chieh Hsu, Louis Liu, Yi-Kan Cheng | 2012-10-09 |
| 8255837 | Methods for cell boundary isolation in double patterning design | Yi-Kan Cheng, Yuan-Te Hou, Yung-Chin Hou, Li-Chun Tien | 2012-08-28 |
| 8245174 | Double patterning friendly lithography method and system | Yi-Kan Cheng, Ru-Gun Liu | 2012-08-14 |
| 8239806 | Routing system and method for double patterning technology | Huang-Yu Chen, Yuan-Te Hou, Gwan Sin Chang, Wen-Ju Yang, Zhe-Wei Jiang +1 more | 2012-08-07 |
| 8227869 | Performance-aware logic operations for generating masks | Chung-Te Lin, Yen-Sen Wang, Yao-Jen Chuang, Gwan Sin Chang | 2012-07-24 |
| 8214773 | Methods for E-beam direct write lithography | Yi-Kan Cheng, Ru-Gun Liu, Chih-Ming Lai | 2012-07-03 |
| 8211807 | Double patterning technology using single-patterning-spacer-technique | Huang-Yu Chen, Ken-Hsien Hsieh, Tsong-Hua Ou, Fang-Yu Fan, Yuan-Te Hou +2 more | 2012-07-03 |
| 8119310 | Mask-shift-aware RC extraction for double patterning design | Yi-Kan Cheng, Hsiao-Shu Chao, Ke-Ying Su, Cheng-Hung Yeh, Dian-Hau Chen +2 more | 2012-02-21 |
| 8122394 | Performance-aware logic operations for generating masks | Chung-Te Lin, Yen-Sen Wang, Yao-Jen Chuang, Gwan Sin Chang | 2012-02-21 |
| 8117575 | System and method for on-chip-variation analysis | Chung-Hsing Wang, Yuan-Te Hou | 2012-02-14 |
| 7994606 | De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits | Cliff Hou, Chia-Lin Cheng | 2011-08-09 |
| 7966596 | Place-and-route layout method with same footprint cells | Chung-Hsing Wang, Ping Li, Chun-Hui Tai, Li-Chun Tien, Gwan Sin Chang | 2011-06-21 |
| 7958465 | Dummy pattern design for reducing device performance drift | Chien-Chih Kuo, Jian-Yi Li, Sheng-Jier Yang | 2011-06-07 |
| 7932566 | Structure and system of mixing poly pitch cell design under default poly pitch design rules | Yung-Chin Hou, Li-Chun Tien, Ping Li, Ta-Pen Guo | 2011-04-26 |
| 7821039 | Layout architecture for improving circuit performance | Li-Chun Tien, Yung-Chin Hou, Chun-Hui Tai, Ta-Pen Guo, Sheng-Hsin Chen +1 more | 2010-10-26 |
| 7808051 | Standard cell without OD space effect in Y-direction | Yung-Chin Hou, Ta-Pen Guo, Li-Chun Tien, Ping Li, Chun-Hui Tai +1 more | 2010-10-05 |
| 7797646 | Method for using mixed multi-Vt devices in a cell-based design | Shine C. Chung, Cliff Hou, Kun-Lung Chen | 2010-09-14 |