Issued Patents All Time
Showing 101–125 of 187 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10380315 | Integrated circuit and method of forming an integrated circuit | Hui-Zhong Zhuang, Ting-Wei Chiang, Li-Chun Tien, Shun Li Chen | 2019-08-13 |
| 10270430 | Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same | Ta-Pen Guo, Chi-Lin Liu, Shang-Chih Hsieh, Jerry Chang Jui Kao, Li-Chun Tien | 2019-04-23 |
| 10270432 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Shang-Chih Hsieh +1 more | 2019-04-23 |
| 10169520 | Method of reconfiguring uncrowned standard cells and semiconductor apparatus including uncrowned and crowned cells | Prasenjit Ray, Meng-Kai Hsu, Wen-Hao Chen, Yuan-Te Hou | 2019-01-01 |
| 10157840 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-Yuan Chang, Li-Chun Tien, Po-Hsiang Huang +6 more | 2018-12-18 |
| 10003342 | Compressor circuit and compressor circuit layout | Chi-Lin Liu, Meng Wang, Shang-Chih Hsieh, Henry Huang, Ji-Yung LIN | 2018-06-19 |
| 9887698 | Internal clock gated cell | Chi-Lin Liu, Shang-Chih Hsieh | 2018-02-06 |
| 9853630 | Skew-tolerant flip-flop | Jerry Chang Jui Kao, Chi-Lin Liu, Shang-Chih Hsieh, Bor-Tyng Lin | 2017-12-26 |
| 9846755 | Method for cell placement in semiconductor layout and system thereof | Ming-Zhang Kuo, Cheng-Chung Lin, Li-Chun Tien, Sang Hoo Dhong, Ta-Pen Guo | 2017-12-19 |
| 9754073 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu | 2017-09-05 |
| 9747402 | Methods for double-patterning-compliant standard cell design | Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang +2 more | 2017-08-29 |
| 9691666 | Layout architecture for performance improvement | Hui-Zhong Zhuang, Li-Chun Tien | 2017-06-27 |
| 9679915 | Integrated circuit with well and substrate contacts | Ming-Zhang Kuo, Ho-Chieh Hsieh, Hui-Zhong Zhuang, Kuo-Feng TSENG, Cheng-Chung Lin +1 more | 2017-06-13 |
| 9672315 | Optimization for circuit migration | Yi-Kan Cheng, Chung-Hsing Wang, Chen-Fu Huang, Hsiao-Shu Chao, Chin-Yu Chiang +3 more | 2017-06-06 |
| 9647452 | Electrostatic discharge protection for level-shifter circuit | Chia-Hui Chen, Chia-Hung Chu, Kuo-Ji Chen, Ming-Hsiang Song | 2017-05-09 |
| 9641161 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Shang-Chih Hsieh +1 more | 2017-05-02 |
| 9608604 | Voltage level shifter with single well voltage | Chung-Hsing Wang, Chun-Hui Tai, Li-Chun Tien, Shun Li Chen | 2017-03-28 |
| 9594866 | Method for checking and fixing double-patterning layout | Dio Wang, Ken-Hsien Hsieh, Huang-Yu Chen, Li-Chun Tien, Ru-Gun Liu | 2017-03-14 |
| 9584099 | Flip flop circuit | Chi-Lin Liu, Shang-Chih Hsieh, Chang-Yu Wu | 2017-02-28 |
| 9558312 | Electromigration resistant standard cell device | Wen-Hao Chen, Yuan-Te Hou, Shen-Feng Chen, Meng-Fu You | 2017-01-31 |
| 9553043 | Interconnect structure having smaller transition layer via | Wen-Hao Chen, Yuan-Te Hou, Fang-Yu Fan, Yu-Hsiang Kao, Dian-Hau Chen +2 more | 2017-01-24 |
| 9543193 | Non-hierarchical metal layers for integrated circuits | Yuan-Te Hou, Shyue-Shyh Lin, Li-Chun Tien, Dian-Hau Chen | 2017-01-10 |
| 9466978 | Electrostatic discharge protection for level-shifter circuit | Chia-Hui Chen, Chia-Hung Chu, Kuo-Ji Chen, Ming-Hsiang Song | 2016-10-11 |
| 9418196 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu | 2016-08-16 |
| 9356583 | Flip-flop circuit | Chi-Lin Liu, Shang-Chih Hsieh, Chang-Yu Wu | 2016-05-31 |