Issued Patents All Time
Showing 126–150 of 187 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9337290 | Layout architecture for performance improvement | Li-Chun Tien, Hui-Zhong Zhuang | 2016-05-10 |
| 9317646 | Masks formed based on integrated circuit layout design having cell that includes extended active region | Li-Chun Tien, Hui-Zhong Zhuang, Chang-Yu Wu | 2016-04-19 |
| 9312260 | Integrated circuits and manufacturing methods thereof | Ali Keshavarzi, Ta-Pen Guo, Helen Shu-Hui Chang, Hsiang-Jen Tseng, Shyue-Shyh Lin +6 more | 2016-04-12 |
| 9292645 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu | 2016-03-22 |
| 9275186 | Optimization for circuit migration | Yi-Kan Cheng, Chung-Hsing Wang, Chen-Fu Huang, Hsiao-Shu Chao, Chin-Yu Chiang +3 more | 2016-03-01 |
| 9213795 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Hui-Zhong Zhuang, Cheng-I Huang +2 more | 2015-12-15 |
| 9203405 | Low-power internal clock gated cell and method | Chi-Lin Liu, Shang-Chih Hsieh, Meng Wang, Chang-Yu Wu | 2015-12-01 |
| 9123565 | Masks formed based on integrated circuit layout design having standard cell that includes extended active region | Li-Chun Tien, Hui-Zhong Zhuang, Chang-Yu Wu | 2015-09-01 |
| 9117882 | Non-hierarchical metal layers for integrated circuits | Yuan-Te Hou, Shyue-Shyh Lin, Li-Chun Tien, Dian-Hau Chen | 2015-08-25 |
| 9105466 | Integrated circuit | Li-Chun Tien, Hui-Zhong Zhuang, Mei-Hui Huang | 2015-08-11 |
| 9035361 | Electromigration resistant standard cell device | Wen-Hao Chen, Yuan-Te Hou, Shen-Feng Chen, Meng-Fu You | 2015-05-19 |
| 8907441 | Methods for double-patterning-compliant standard cell design | Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang +2 more | 2014-12-09 |
| 8898600 | Layout optimization for integrated design | Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu | 2014-11-25 |
| 8813016 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Hui-Zhong Zhuang, Cheng-I Huang +2 more | 2014-08-19 |
| 8799834 | Self-aligned multiple patterning layout design | Huang-Yu Chen, Li-Chun Tien, Ken-Hsien Hsieh, Jhih-Jian Wang, Chin-Chang Hsu +3 more | 2014-08-05 |
| 8775977 | Decomposition and marking of semiconductor device design layout in double patterning lithography | Chin-Chang Hsu, Wen-Ju Yang, Hsiao-Shu Chao, Yi-Kan Cheng | 2014-07-08 |
| 8671367 | Integrated circuit design in optical shrink technology node | Chung-Hsing Wang, Yung-Chin Hou, Lie-Szu Juang | 2014-03-11 |
| 8631366 | Integrated circuit design using DFM-enhanced architecture | Yung-Chin Hou, Li-Chun Tien, Yi-Kan Cheng, Chun-Hui Tai, Ta-Pen Guo +1 more | 2014-01-14 |
| 8607172 | Integrated circuits and methods of designing the same | Li-Chun Tien, Hui-Zhong Zhuang, Mei-Hui Huang | 2013-12-10 |
| 8584052 | Cell layout for multiple patterning technology | Huang-Yu Chen, Yuan-Te Hou, Ken-Hsien Hsieh, Ru-Gun Liu | 2013-11-12 |
| 8504972 | Standard cells having flexible layout architecture/boundaries | Yung-Chin Hou, David B. Scott, Li-Chun Tien | 2013-08-06 |
| 8443306 | Planar compatible FDSOI design architecture | Sang Hoo Dhong, Jiann-Tyng Tzeng, Kushare Mangesh Babaji, Ramakrishnan Krishnan, Ta-Pen Guo | 2013-05-14 |
| 8431968 | Electromigration resistant standard cell device | Wen-Hao Chen, Yuan-Te Hou, Shen-Feng Chen, Meng-Fu You | 2013-04-30 |
| 8431985 | Layout and process of forming contact plugs | Yung-Chin Hou, Shyue-Shyh Lin, Li-Chun Tien | 2013-04-30 |
| 8434032 | Method of generating an intellectual property block design kit, method of generating an integrated circuit design, and simulation system for the integrated circuit design | Yun-Han Lee, Wei-Li Chen, Tan-Li Chou, Kheng Guan (Nigel) Tan, Shi-Hung Wang | 2013-04-30 |