Issued Patents All Time
Showing 25 most recent of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11197387 | Server apparatus and fixing mechanism thereof | Hui Liu, Chia-Hsin Liu, Zhi-Tao Yu | 2021-12-07 |
| 10993346 | Electronic device capable of installing different modules and case module thereof | Yi-Sing Syu | 2021-04-27 |
| 8286119 | Systematic method for variable layout shrink | Louis Liu, Lee-Chung Lu, Yi-Kan Cheng | 2012-10-09 |
| 8030181 | Electrical fuse circuit for security applications | Shine C. Chung, Fu-Lung Hsueh | 2011-10-04 |
| 7821041 | Electrical fuse circuit for security applications | Shine C. Chung, Fu-Lung Hsueh | 2010-10-26 |
| 7634707 | Error detection/correction method | Wingyu Leung | 2009-12-15 |
| 7505345 | Circuit and method for an SRAM with two phase word line pulse | Chia-Wei Wang, Cheng Hung Lee, Hung-Jen Liao | 2009-03-17 |
| 7353438 | Transparent error correcting memory | Wingyu Leung, Kit S. Tam, Mikolaj Tworek | 2008-04-01 |
| 7323379 | Fabrication process for increased capacitance in an embedded DRAM memory | Dennis Sinitsky | 2008-01-29 |
| 7206913 | High speed memory system | Wingyu Leung | 2007-04-17 |
| 7056785 | Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same | — | 2006-06-06 |
| 7051264 | Error correcting memory and method of operating same | Wingyu Leung | 2006-05-23 |
| 6964895 | Method of fabricating vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region | — | 2005-11-15 |
| 6913964 | Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region | — | 2005-07-05 |
| 6841821 | Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same | — | 2005-01-11 |
| 6808169 | Non-volatile memory with crown electrode to increase capacitance between control gate and floating gate | Wingyu Leung | 2004-10-26 |
| 6784048 | Method of fabricating a DRAM cell having a thin dielectric access transistor and a thick dielectric storage | Wingyu Leung | 2004-08-31 |
| 6754746 | Memory array with read/write methods | Wingyu Leung, Winston Lee | 2004-06-22 |
| 6744676 | DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same | Wingyu Leung | 2004-06-01 |
| 6717864 | Latched sense amplifiers as high speed memory in a memory system | Wing Yu Leung | 2004-04-06 |
| 6686624 | Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region | — | 2004-02-03 |
| 6661042 | One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region | — | 2003-12-09 |
| 6654295 | Reduced topography DRAM cell fabricated using a modified logic process and method for operating same | Wingyu Leung | 2003-11-25 |
| 6642098 | DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same | Wingyu Leung | 2003-11-04 |
| 6573548 | DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same | Wingyu Leung | 2003-06-03 |