Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8375347 | Driven metal critical dimension (CD) biasing | Lee-Chung Lu, Yao-Ching Ku | 2013-02-12 |
| 8365115 | System and method for performance modeling of integrated circuits | Morly Hsieh, Dei-Pei Liu | 2013-01-29 |
| 8286119 | Systematic method for variable layout shrink | Fu-Chieh Hsu, Lee-Chung Lu, Yi-Kan Cheng | 2012-10-09 |
| 7853905 | Performing early DFT-aware prototyping of a design | Kit Lam Cheong, Ping-Chih Wu, Weibin Ding, Yiqun Ding | 2010-12-14 |
| 7494846 | Design techniques for stacking identical memory dies | Chao-Shun Hsu, Clinton Chao, Mark Shane Peng | 2009-02-24 |
| 6925614 | System and method for protecting and integrating silicon intellectual property (IP) in an integrated circuit (IC) | Cheng Lu, Jun-Jyeh Hsiao | 2005-08-02 |
| 6855967 | Utilization of MACRO power routing area for buffer insertion | Chien-Wen Chen | 2005-02-15 |
| 6818931 | Chip design with power rails under transistors | Hsiao-Hsuan Chou | 2004-11-16 |
| 6668360 | Automatic integrated circuit design kit qualification service provided through the internet | — | 2003-12-23 |
| 6583045 | Chip design with power rails under transistors | Hsiao-Hsuan Chou | 2003-06-24 |
| 6492205 | Utilization of macro power routing area for buffer insertion | Chien-Wen Chen | 2002-12-10 |
| 4933860 | Method for fabricating a radio frequency integrated circuit and product formed thereby | — | 1990-06-12 |