Issued Patents All Time
Showing 26–50 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6512691 | Non-volatile memory embedded in a conventional logic process | Wingyu Leung | 2003-01-28 |
| 6509595 | DRAM cell fabricated using a modified logic process and method for operating same | Wingyu Leung | 2003-01-21 |
| 6510492 | Apparatus for controlling data transfer between a bus and memory array and method for operating same | Wingyu Leung | 2003-01-21 |
| 6483755 | Memory modules with high speed latched sense amplifiers | Wing Yu Leung | 2002-11-19 |
| 6468855 | Reduced topography DRAM cell fabricated using a modified logic process and method for operating same | Wingyu Leung | 2002-10-22 |
| 6457108 | Method of operating a system-on-a-chip including entering a standby state in a non-volatile memory while operating the system-on-a-chip from a volatile memory | Wingyu Leung | 2002-09-24 |
| 6442060 | High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process | Wingyu Leung | 2002-08-27 |
| 6425046 | Method for using a latched sense amplifier in a memory module as a high-speed cache memory | Wing Yu Leung | 2002-07-23 |
| 6393504 | Dynamic address mapping and redundancy in a modular memory device | Wingyu Leung, Winston Lee | 2002-05-21 |
| 6370052 | Method and structure of ternary CAM cell in logic process | Wingyu Leung | 2002-04-09 |
| 6329240 | Non-volatile memory cell and methods of fabricating and operating same | Wingyu Leung | 2001-12-11 |
| 6295593 | Method of operating memory array with write buffers and related apparatus | Wingyu Leung | 2001-09-25 |
| 6272577 | Data processing system with master and slave devices and asymmetric signal swing bus | Wingyu Leung, Winston Lee | 2001-08-07 |
| 6147914 | On-chip word line voltage generation for DRAM embedded in logic process | Wingyu Leung | 2000-11-14 |
| 6128700 | System utilizing a DRAM array as a next level cache memory and method for operating same | Wingyu Leung | 2000-10-03 |
| 6075720 | Memory cell for DRAM embedded in logic | Wingyu Leung | 2000-06-13 |
| 5999474 | Method and apparatus for complete hiding of the refresh of a semiconductor memory | Wingyu Leung | 1999-12-07 |
| 5940088 | Method and structure for data traffic reduction for display refresh | — | 1999-08-17 |
| 5923593 | Multi-port DRAM cell and memory system using same | Wingyu Leung | 1999-07-13 |
| 5843799 | Circuit module redundancy architecture process | Wingyu Leung | 1998-12-01 |
| 5831467 | Termination circuit with power-down mode for use in circuit module architecture | Wingyu Leung | 1998-11-03 |
| 5829026 | Method and structure for implementing a cache memory using a DRAM array | Wingyu Leung | 1998-10-27 |
| 5790138 | Method and structure for improving display data bandwidth in a unified memory architecture system | — | 1998-08-04 |
| 5737587 | Resynchronization circuit for circuit module architecture | Wingyu Leung, Winston Lee | 1998-04-07 |
| 5729152 | Termination circuits for reduced swing signal lines and methods for operating same | Wingyu Leung, Winston Lee | 1998-03-17 |