Issued Patents All Time
Showing 1–25 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12402391 | Stressed material within gate cut region | Huimei Zhou, Andrew M. Greene, Michael P. Belyansky, Oleg Gluschenkov, Robert R. Robison +2 more | 2025-08-26 |
| 12050206 | Pneumatic grip systems and material testing systems including pneumatic grip systems | Keith Tremblay | 2024-07-30 |
| 11791398 | Nano multilayer carbon-rich low-k spacer | Donald F. Canaperi, Thomas J. Haigh, Jr., Eric R. Miller, Son V. Nguyen | 2023-10-17 |
| 11592375 | Collision mitigation apparatus material testing systems having collision mitigation apparatus | Jaron Burnworth | 2023-02-28 |
| 11322408 | Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer | Nicolas Loubet, Choonghyun Lee | 2022-05-03 |
| 11189532 | Dual width finned semiconductor structure | Yi Song, Jay William Strane, Eric R. Miller, Fee Li Lie | 2021-11-30 |
| 11164958 | Nanosheet transistor having a strained channel with strain-preserving multi-segmented source/drain regions | Shogo Mochizuki, Nicolas Loubet, Zhenxing Bi | 2021-11-02 |
| 11114382 | Middle-of-line interconnect having low metal-to-metal interface resistance | Alex Varghese, Su Chen Fan | 2021-09-07 |
| 11056537 | Self-aligned gate contact integration with metal resistor | Xin Miao, Ruilong Xie, Kangguo Cheng | 2021-07-06 |
| 10937892 | Nano multilayer carbon-rich low-k spacer | Donald F. Canaperi, Thomas J. Haigh, Jr., Eric R. Miller, Son V. Nguyen | 2021-03-02 |
| 10910273 | Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer | Nicolas Loubet, Choonghyun Lee | 2021-02-02 |
| 10832973 | Stress modulation of nFET and pFET fin structures | Huimei Zhou, Kangguo Cheng, Michael P. Belyansky, Oleg Gluschenkov, James J. Kelly +1 more | 2020-11-10 |
| 10734245 | Highly selective dry etch process for vertical FET STI recess | Zhenxing Bi, Muthumanickam Sankarapandian, Michael P. Belyansky | 2020-08-04 |
| 10672668 | Dual width finned semiconductor structure | Yi Song, Jay William Strane, Eric R. Miller, Fee Li Lie | 2020-06-02 |
| 10665512 | Stress modulation of nFET and pFET fin structures | Huimei Zhou, Kangguo Cheng, Michael P. Belyansky, Oleg Gluschenkov, James J. Kelly +1 more | 2020-05-26 |
| 10586733 | Multi-level air gap formation in dual-damascene structure | Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer | 2020-03-10 |
| 10586700 | Protection of low temperature isolation fill | Michael P. Belyansky, Dechao Guo, Devendra K. Sadana, Jay William Strane | 2020-03-10 |
| 10535550 | Protection of low temperature isolation fill | Michael P. Belyansky, Dechao Guo, Devendra K. Sadana, Jay William Strane | 2020-01-14 |
| 10224239 | Multi-level air gap formation in dual-damascene structure | Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer | 2019-03-05 |
| 10204827 | Multi-level air gap formation in dual-damascene structure | Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer | 2019-02-12 |
| 9859212 | Multi-level air gap formation in dual-damascene structure | Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer | 2018-01-02 |
| 8673725 | Multilayer sidewall spacer for seam protection of a patterned structure | David L. O'Meara, Anthony Dip, Aelan Mosden, Pao-Hwa Chou | 2014-03-18 |
| 8664102 | Dual sidewall spacer for seam protection of a patterned structure | David L. O'Meara, Anthony Dip, Aelan Mosden, Pao-Hwa Chou | 2014-03-04 |
| 7998871 | Mask forming and implanting methods using implant stopping layer | Katherina Babich, Todd C. Bailey, Ryan P. Deschner | 2011-08-16 |
| 7968270 | Process of making a semiconductor device using multiple antireflective materials | Marie Angelopoulos, Katherina Babich, Sean D. Burns, Allen H. Gabor, Scott D. Halle +2 more | 2011-06-28 |