Issued Patents All Time
Showing 76–100 of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8525309 | Flip-chip QFN structure using etched lead frame | Chok J. Chia, Qwai H. Low, Kishor Desai | 2013-09-03 |
| 8498131 | Interconnect structure | Raymond Albert Fillion, Kevin Matthew Durocher, Richard Joseph Saia | 2013-07-30 |
| 8345508 | Large area modular sensor array assembly and method for making the same | Robert Gideon Wodnicki, Rayette Ann Fisher, Shubhra Bansal, Albert Taesung Byun | 2013-01-01 |
| 8296940 | Method of forming a micro pin hybrid interconnect array | John Eric Tkaczyk, Brian David Yanoff, Tan Zhang | 2012-10-30 |
| 8207652 | Ultrasound transducer with improved acoustic performance | Charles Edward Baumgartner, Jean-Francois Gelly, Lowell Scott Smith, Frederic Lanteri, Stephen Edwardsen +1 more | 2012-06-26 |
| 7956457 | System and apparatus for venting electronic packages and method of making same | Raymond Albert Fillion, Kevin Matthew Durocher, Elizabeth Ann Burke, Thomas Bert Gorczyca | 2011-06-07 |
| 7892176 | Monitoring or imaging system with interconnect structure for large area sensor array | Robert Gideon Wodnicki, David Martin Mills, Rayette Ann Fisher | 2011-02-22 |
| 7781238 | Methods of making and using integrated and testable sensor array | Robert Gideon Wodnicki, Stacey Joy Kennerly, Wei-Cheng Tian, Kevin Matthew Durocher, David Martin Mills +1 more | 2010-08-24 |
| 7606346 | CT detector module construction | John Eric Tkaczyk, Jonathan David Short, Yanfeng Du, James Wilson Rose | 2009-10-20 |
| 7451651 | Modular sensor assembly and methods of fabricating the same | Rayette Ann Fisher, David Martin Mills, Scott D. Cogan, David Richard Esler, Robert Gideon Wodnicki +1 more | 2008-11-18 |
| 7250330 | Method of making an electronic package | David L. Thomas | 2007-07-31 |
| 6994243 | Low temperature solder chip attach structure and process to produce a high temperature interconnection | Joseph M. Milewski | 2006-02-07 |
| 6989607 | Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers | Krishna Darbha, Miguel A. Jimarez, Matthew Reiss, Sanjeev Sathe | 2006-01-24 |
| 6946329 | Methods of making and using a floating interposer | Mark V. Pierson, Jennifer Sweterlitsch, Thurston Bryce Youngs, Jr. | 2005-09-20 |
| 6847118 | Low temperature solder chip attach structure | Joseph M. Milewski | 2005-01-25 |
| 6821814 | Method for joining a semiconductor chip to a chip carrier substrate and resulting chip package | William Rena LaFontaine, Jr., Paul Mescher | 2004-11-23 |
| 6774315 | Floating interposer | Mark V. Pierson, Jennifer Sweterlitsch, Thurston Bryce Youngs, Jr. | 2004-08-10 |
| 6672500 | Method for producing a reliable solder joint interconnection | David V. Caletka, Kevin Knadle | 2004-01-06 |
| 6667557 | Method of forming an apparatus to reduce thermal fatigue stress on flip chip solder connections | David J. Alcoe, Eric A. Johnson, Matthew Reiss | 2003-12-23 |
| 6639302 | Stress reduction in flip-chip PBGA packaging by utilizing segmented chip carries | Krishna Darbha, Miguel A. Jimarez, Matthew Reiss, Sanjeev Sathe | 2003-10-28 |
| 6570259 | Apparatus to reduce thermal fatigue stress on flip chip solder connections | David J. Alcoe, Eric A. Johnson, Matthew Reiss | 2003-05-27 |
| 6559666 | Method and device for semiconductor testing using electrically conductive adhesives | William E. Bernier, Michael A. Gaynes, Wayne J. Howell, Mark V. Pierson, Ajit K. Trivedi | 2003-05-06 |
| 6516513 | Method of making a CTE compensated chip interposer | Cynthia S. Milkovich, Mark V. Pierson | 2003-02-11 |
| 6517662 | Process for making semiconductor chip assembly | Thomas M. Culnane, Michael A. Gaynes, Ramesh R. Kodnani, Mark V. Pierson | 2003-02-11 |
| 6399892 | CTE compensated chip interposer | Cynthia S. Milkovich, Mark V. Pierson | 2002-06-04 |