Issued Patents All Time
Showing 151–175 of 360 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11139296 | CMOS circuit with vertically oriented n-type transistor and method of providing same | Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Ravi Pillarisetty | 2021-10-05 |
| 11107890 | FINFET transistor having a doped subfin structure to reduce channel to substrate leakage | Gilbert Dewey, Matthew V. Metz, Anand S. Murthy, Chandra S. Mohapatra, Tahir Ghani +2 more | 2021-08-31 |
| 11101377 | Transistor device with heterogeneous channel structure bodies and method of providing same | Abhishek A. Sharma, Gilbert Dewey, Van H. Le, Ravi Pillarisetty | 2021-08-24 |
| 11101376 | Non-planar transition metal dichalcogenide devices | Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Gilbert Dewey | 2021-08-24 |
| 11101270 | Techniques and mechanisms for operation of stacked transistors | Ravi Pillarisetty, Marko Radosavljevic, Van H. Le, Jack T. Kavalieros | 2021-08-24 |
| 11088204 | Three terminal selectors for memory applications and their methods of fabrication | Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros | 2021-08-10 |
| 11081483 | CMOS circuit with a group III-nitride transistor and method of providing same | Ravi Pillarisetty, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Van H. Le | 2021-08-03 |
| 11075202 | Bottom fin trim isolation aligned with top gate for stacked device architectures | Aaron D. Lilak, Gilbert Dewey, Patrick Morrow, Rishabh Mehandru | 2021-07-27 |
| 11075198 | Stacked transistor architecture having diverse fin geometry | Aaron D. Lilak, Cheng-Ying Huang, Gilbert Dewey, Rishabh Mehandru | 2021-07-27 |
| 11049773 | Art trench spacers to enable fin release for non-lattice matched channels | Gilbert Dewey, Matthew V. Metz, Sean T. Ma, Cheng-Ying Huang, Tahir Ghani +4 more | 2021-06-29 |
| 11031499 | Germanium transistor structure with underlap tip to reduce gate induced barrier lowering/short channel effect while minimizing impact on drive current | Van H. Le, Matthew V. Metz, Benjamin Chu-Kung, Ashish Agrawal, Jack T. Kavalieros | 2021-06-08 |
| 11024714 | Nanowire transistor fabrication with hardmask layers | Seung Hoon Sung, Seiyon Kim, Kelin J. Kuhn, Jack T. Kavalieros | 2021-06-01 |
| 11017843 | Thin film transistors for memory cell array layer selection | Abhishek A. Sharma, Gilbert Dewey, Van H. Le, Matthew V. Metz, Jack T. Kavalieros | 2021-05-25 |
| 10991799 | Silicon and silicon germanium nanowire structures | Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles +3 more | 2021-04-27 |
| 10957769 | High-mobility field effect transistors with wide bandgap fin cladding | Sean T. Ma, Chandra S. Mohapatra, Gilbert Dewey, Harold W. Kennel, Matthew V. Metz +3 more | 2021-03-23 |
| 10950733 | Deep gate-all-around semiconductor device having germanium or group III-V active layer | Ravi Pillarisetty, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros +5 more | 2021-03-16 |
| 10930766 | Ge NANO wire transistor with GAAS as the sacrificial layer | Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Sanaz K. Gardner | 2021-02-23 |
| 10903364 | Semiconductor device with released source and drain | Sanaz K. Gardner, Chandra S. Mohapatra, Matthew V. Metz, Gilbert Dewey, Sean T. Ma +3 more | 2021-01-26 |
| 10892335 | Device isolation by fixed charge | Sean T. Ma, Gilbert Dewey, Aaron D. Lilak, Justin R. Weber, Harold W. Kennel +5 more | 2021-01-12 |
| 10886408 | Group III-V material transistors employing nitride-based dopant diffusion barrier layer | Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Gilbert Dewey +4 more | 2021-01-05 |
| 10879365 | Transistors with non-vertical gates | Cheng-Ying Huang, Sean T. Ma, Gilbert Dewey, Matthew V. Metz, Harold W. Kennel +3 more | 2020-12-29 |
| 10861939 | Stiff quantum layers to slow and or stop defect propagation | Matthew V. Metz, Gilbert Dewey, Harold W. Kennel, Cheng-Ying Huang, Sean T. Ma | 2020-12-08 |
| 10854752 | High mobility strained channels for fin-based NMOS transistors | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy +1 more | 2020-12-01 |
| 10847619 | Supperlatice channel included in a trench | Cheng-Ying Huang, Matthew V. Metz, Gilbert Dewey, Jack T. Kavalieros | 2020-11-24 |
| 10840352 | Nanowire transistors with embedded dielectric spacers | Seung Hoon Sung, Jack T. Kavalieros, Sanaz K. Gardner | 2020-11-17 |